Lines Matching +full:ast2500 +full:- +full:scu
4 * SPDX-License-Identifier: GPL-2.0
8 #include <clk-uclass.h>
13 #include <dt-bindings/clock/ast2500-scu.h>
33 * For H-PLL and M-PLL the formula is
35 * M - Numerator
36 * N - Denumerator
37 * P - Post Divider
40 * D-PLL and D2-PLL have extra divider (OD + 1), which is not
50 * Get the rate of the M-PLL clock from input clock frequency and
51 * the value of the M-PLL Parameter Register.
65 * Get the rate of the H-PLL clock from input clock frequency and
66 * the value of the H-PLL Parameter Register.
79 static ulong ast2500_get_clkin(struct ast2500_scu *scu) in ast2500_get_clkin() argument
81 return readl(&scu->hwstrap) & SCU_HWSTRAP_CLKIN_25MHZ in ast2500_get_clkin()
88 * @scu SCU registers
89 * @uart_index UART index, 1-5
93 static ulong ast2500_get_uart_clk_rate(struct ast2500_scu *scu, int uart_index) in ast2500_get_uart_clk_rate() argument
96 * ast2500 datasheet is very confusing when it comes to UART clocks, in ast2500_get_uart_clk_rate()
104 if (readl(&scu->misc_ctrl2) & in ast2500_get_uart_clk_rate()
105 (1 << (uart_index - 1 + SCU_MISC2_UARTCLK_SHIFT))) in ast2500_get_uart_clk_rate()
110 if (readl(&scu->misc_ctrl1) & SCU_MISC_UARTCLK_DIV13) in ast2500_get_uart_clk_rate()
118 struct ast2500_clk_priv *priv = dev_get_priv(clk->dev); in ast2500_clk_get_rate()
119 ulong clkin = ast2500_get_clkin(priv->scu); in ast2500_clk_get_rate()
122 switch (clk->id) { in ast2500_clk_get_rate()
130 readl(&priv->scu->h_pll_param)); in ast2500_clk_get_rate()
134 readl(&priv->scu->m_pll_param)); in ast2500_clk_get_rate()
138 ulong apb_div = 4 + 4 * ((readl(&priv->scu->clk_sel1) in ast2500_clk_get_rate()
142 readl(&priv-> in ast2500_clk_get_rate()
143 scu->h_pll_param)); in ast2500_clk_get_rate()
148 rate = ast2500_get_uart_clk_rate(priv->scu, 1); in ast2500_clk_get_rate()
151 rate = ast2500_get_uart_clk_rate(priv->scu, 2); in ast2500_clk_get_rate()
154 rate = ast2500_get_uart_clk_rate(priv->scu, 3); in ast2500_clk_get_rate()
157 rate = ast2500_get_uart_clk_rate(priv->scu, 4); in ast2500_clk_get_rate()
160 rate = ast2500_get_uart_clk_rate(priv->scu, 5); in ast2500_clk_get_rate()
163 return -ENOENT; in ast2500_clk_get_rate()
170 * @input_rate - the rate of input clock in Hz
171 * @requested_rate - desired output rate in Hz
172 * @div - this is an IN/OUT parameter, at input all fields of the config
209 if (new_rate_khz - rate_khz < delta) { in ast2500_calc_clock_config()
210 delta = new_rate_khz - rate_khz; in ast2500_calc_clock_config()
221 static ulong ast2500_configure_ddr(struct ast2500_scu *scu, ulong rate) in ast2500_configure_ddr() argument
223 ulong clkin = ast2500_get_clkin(scu); in ast2500_configure_ddr()
233 mpll_reg = readl(&scu->m_pll_param); in ast2500_configure_ddr()
240 ast_scu_unlock(scu); in ast2500_configure_ddr()
241 writel(mpll_reg, &scu->m_pll_param); in ast2500_configure_ddr()
242 ast_scu_lock(scu); in ast2500_configure_ddr()
247 static ulong ast2500_configure_mac(struct ast2500_scu *scu, int index) in ast2500_configure_mac() argument
249 ulong clkin = ast2500_get_clkin(scu); in ast2500_configure_mac()
251 readl(&scu->h_pll_param)); in ast2500_configure_mac()
262 hwstrap = readl(&scu->hwstrap); in ast2500_configure_mac()
290 return -EINVAL; in ast2500_configure_mac()
293 ast_scu_unlock(scu); in ast2500_configure_mac()
294 clrsetbits_le32(&scu->clk_sel1, SCU_MACCLK_MASK, in ast2500_configure_mac()
295 ((divisor - 2) / 2) << SCU_MACCLK_SHIFT); in ast2500_configure_mac()
298 * Disable MAC, start its clock and re-enable it. in ast2500_configure_mac()
302 setbits_le32(&scu->sysreset_ctrl1, reset_bit); in ast2500_configure_mac()
304 clrbits_le32(&scu->clk_stop_ctrl1, clkstop_bit); in ast2500_configure_mac()
306 clrbits_le32(&scu->sysreset_ctrl1, reset_bit); in ast2500_configure_mac()
310 &scu->clk_duty_sel); in ast2500_configure_mac()
312 ast_scu_lock(scu); in ast2500_configure_mac()
317 static ulong ast2500_configure_d2pll(struct ast2500_scu *scu, ulong rate) in ast2500_configure_d2pll() argument
336 ulong clkin = ast2500_get_clkin(scu); in ast2500_configure_d2pll()
339 ast_scu_unlock(scu); in ast2500_configure_d2pll()
342 | SCU_D2PLL_EXT1_RESET, &scu->d2_pll_ext_param[0]); in ast2500_configure_d2pll()
346 * This would disconnect it from D2-PLL. in ast2500_configure_d2pll()
348 clrsetbits_le32(&scu->misc_ctrl1, SCU_MISC_D2PLL_OFF, in ast2500_configure_d2pll()
357 &scu->d2_pll_param); in ast2500_configure_d2pll()
359 clrbits_le32(&scu->d2_pll_ext_param[0], in ast2500_configure_d2pll()
362 clrsetbits_le32(&scu->misc_ctrl2, in ast2500_configure_d2pll()
368 writel(clk_delay_settings | SCU_MICDS_RGMIIPLL, &scu->mac_clk_delay); in ast2500_configure_d2pll()
369 writel(clk_delay_settings, &scu->mac_clk_delay_100M); in ast2500_configure_d2pll()
370 writel(clk_delay_settings, &scu->mac_clk_delay_10M); in ast2500_configure_d2pll()
372 ast_scu_lock(scu); in ast2500_configure_d2pll()
379 struct ast2500_clk_priv *priv = dev_get_priv(clk->dev); in ast2500_clk_set_rate()
382 switch (clk->id) { in ast2500_clk_set_rate()
385 new_rate = ast2500_configure_ddr(priv->scu, rate); in ast2500_clk_set_rate()
388 new_rate = ast2500_configure_d2pll(priv->scu, rate); in ast2500_clk_set_rate()
391 return -ENOENT; in ast2500_clk_set_rate()
399 struct ast2500_clk_priv *priv = dev_get_priv(clk->dev); in ast2500_clk_enable()
401 switch (clk->id) { in ast2500_clk_enable()
408 ast2500_configure_mac(priv->scu, 1); in ast2500_clk_enable()
411 ast2500_configure_mac(priv->scu, 2); in ast2500_clk_enable()
414 ast2500_configure_d2pll(priv->scu, D2PLL_DEFAULT_RATE); in ast2500_clk_enable()
416 return -ENOENT; in ast2500_clk_enable()
432 priv->scu = devfdt_get_addr_ptr(dev); in ast2500_clk_probe()
433 if (IS_ERR(priv->scu)) in ast2500_clk_probe()
434 return PTR_ERR(priv->scu); in ast2500_clk_probe()
444 ret = device_bind_driver(gd->dm_root, "ast_sysreset", "reset", &dev); in ast2500_clk_bind()
452 { .compatible = "aspeed,ast2500-scu" },