352 static void ahci_fill_cmd_slot(struct ahci_ioports *pp, u32 cmd_slot, u32 opts)  in ahci_fill_cmd_slot()  argument
354 	struct ahci_cmd_hdr *cmd_hdr = (struct ahci_cmd_hdr *)(pp->cmd_slot +  in ahci_fill_cmd_slot()
355 					AHCI_CMD_SLOT_SZ * cmd_slot);  in ahci_fill_cmd_slot()
360 	pp->cmd_slot->tbl_addr = cpu_to_le32((u32)pp->cmd_tbl & 0xffffffff);  in ahci_fill_cmd_slot()
362 	pp->cmd_slot->tbl_addr_hi =  in ahci_fill_cmd_slot()
376 	int sg_count = 0, cmd_slot = 0;  in ahci_exec_ata_cmd()  local
378 	cmd_slot = AHCI_GET_CMD_SLOT(readl(&port_mmio->ci));  in ahci_exec_ata_cmd()
379 	if (32 == cmd_slot) {  in ahci_exec_ata_cmd()
399 	ahci_fill_cmd_slot(pp, cmd_slot, opts);  in ahci_exec_ata_cmd()
401 	flush_cache((int)(pp->cmd_slot), AHCI_PORT_PRIV_DMA_SZ);  in ahci_exec_ata_cmd()
402 	writel_with_flush(1 << cmd_slot, &port_mmio->ci);  in ahci_exec_ata_cmd()
405 				      0x1 << cmd_slot)) {  in ahci_exec_ata_cmd()
409 	invalidate_dcache_range((int)(pp->cmd_slot),  in ahci_exec_ata_cmd()
410 				(int)(pp->cmd_slot)+AHCI_PORT_PRIV_DMA_SZ);  in ahci_exec_ata_cmd()
412 	      pp->cmd_slot->status);  in ahci_exec_ata_cmd()
464 	pp->cmd_slot = (struct ahci_cmd_hdr *)mem;  in ahci_port_start()
465 	debug("cmd_slot = 0x%x\n", (unsigned int) pp->cmd_slot);  in ahci_port_start()
485 	writel_with_flush((u32)pp->cmd_slot, &port_mmio->clb);  in ahci_port_start()