Lines Matching +full:de +full:- +full:asserted

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5 - compatible		: should be "cadence,qspi".
6 - reg			: 1.Physical base address and size of SPI registers map.
8 - clocks		: Clock phandles (see clock bindings for details).
9 - sram-size		: spi controller sram size.
10 - status		: enable in requried dts.
13 --------------------------
15 - spi-max-frequency	: Max supported spi frequency.
16 - page-size		: Flash page size.
17 - block-size		: Flash memory block size.
18 - tshsl-ns		: Added delay in master reference clocks (ref_clk) for
20 			  are de-asserted between transactions.
21 - tsd2d-ns		: Delay in master reference clocks (ref_clk) between one
22 			  chip select being de-activated and the activation of
24 - tchsh-ns		: Delay in master reference clocks between last bit of
25 			  current transaction and de-asserting the device chip
27 - tslch-ns		: Delay in master reference clocks between setting