doc/SPI/README.dual-flash

1 SPI/QSPI Dual flash connection modes:
4 This describes how SPI/QSPI flash memories are connected to a given
5 controller in a single chip select line.
8 to a given controller with single chip select line, but there are some
10 connected with a single chip select line from a controller.
12 "dual_flash" from include/spi.h describes these types of connection mode
15 --------------------
17        - single spi flash memory connected with single chip select line.
19   +------------+             CS         +---------------+
20   |            |----------------------->|               |
21   | Controller |         I0[3:0]        | Flash memory  |
22   | SPI/QSPI   |<======================>| (SPI/QSPI)    |
24   |            |----------------------->|               |
25   +------------+                        +---------------+
28        - dual spi/qspi flash memories are connected with a single chipselect
30        - xilinx zynq qspi controller has implemented this feature [1]
32   +------------+        CS             +---------------+
33   |            |---------------------->|               |
36   |            |            |     CLK  | (SPI/QSPI)    |
37   |            |            |    +---->|               |
38   | Controller |        CS  |    |     +---------------+
39   | SPI/QSPI   |------------|----|---->|               |
42   |            |          CLK    |     | (SPI/QSPI)    |
43   |            |-----------------+---->|               |
44   +------------+                       +---------------+
46        - two memory flash devices should has same hw part attributes (like size,
48        - Configurations:
50                Enable U_PAGE[BIT:28] if U_PAGE flag set - upper memory
51                Disable U_PAGE[BIT:28] if U_PAGE flag unset - lower memory
52        - Operation:
58 	- dual spi/qspi flash memories are connected with a single chipselect
60 	- xilinx zynq qspi controller has implemented this feature [1]
62   +-------------+           CS		+---------------+
63   |		|---------------------->|		|
66   |		|	   CLK		| (SPI/QSPI)	|
67   |		|---------------------->|		|
68   | Controller	|	    CS		+---------------+
69   | SPI/QSPI	|---------------------->|		|
72   |		|	   CLK		| (SPI/QSPI)	|
73   |		|---------------------->|		|
74   +-------------+			+---------------+
76 	- two memory flash devices should has same hw part attributes (like size,
78 	- Configurations:
80 	- Operation:
84 Note: Technically there is only one CS line from the controller, but
85 zynq qspi controller has an internal hw logic to enable additional CS
86 when controller is configured for dual memories.
88 [1] http://www.xilinx.com/support/documentation/user_guides/ug585-Zynq-7000-TRM.pdf
90 --
92 05-01-2014.