Lines Matching +full:single +full:- +full:chip
5 controller in a single chip select line.
7 Current spi_flash framework supports, single flash memory connected
8 to a given controller with single chip select line, but there are some
10 connected with a single chip select line from a controller.
15 --------------------
17 - single spi flash memory connected with single chip select line.
19 +------------+ CS +---------------+
20 | |----------------------->| |
24 | |----------------------->| |
25 +------------+ +---------------+
28 - dual spi/qspi flash memories are connected with a single chipselect
30 - xilinx zynq qspi controller has implemented this feature [1]
32 +------------+ CS +---------------+
33 | |---------------------->| |
37 | | | +---->| |
38 | Controller | CS | | +---------------+
39 | SPI/QSPI |------------|----|---->| |
43 | |-----------------+---->| |
44 +------------+ +---------------+
46 - two memory flash devices should has same hw part attributes (like size,
48 - Configurations:
50 Enable U_PAGE[BIT:28] if U_PAGE flag set - upper memory
51 Disable U_PAGE[BIT:28] if U_PAGE flag unset - lower memory
52 - Operation:
58 - dual spi/qspi flash memories are connected with a single chipselect
60 - xilinx zynq qspi controller has implemented this feature [1]
62 +-------------+ CS +---------------+
63 | |---------------------->| |
67 | |---------------------->| |
68 | Controller | CS +---------------+
69 | SPI/QSPI |---------------------->| |
73 | |---------------------->| |
74 +-------------+ +---------------+
76 - two memory flash devices should has same hw part attributes (like size,
78 - Configurations:
80 - Operation:
88 [1] http://www.xilinx.com/support/documentation/user_guides/ug585-Zynq-7000-TRM.pdf
90 --
92 05-01-2014.