doc/SPI/README.dual-flash

5 controller in a single chip select line.
7 Current spi_flash framework supports, single flash memory connected
8 to a given controller with single chip select line, but there are some
10 connected with a single chip select line from a controller.
15 --------------------
17        - single spi flash memory connected with single chip select line.
19   +------------+             CS         +---------------+
20   |            |----------------------->|               |
21   | Controller |         I0[3:0]        | Flash memory  |
24   |            |----------------------->|               |
25   +------------+                        +---------------+
28        - dual spi/qspi flash memories are connected with a single chipselect
30        - xilinx zynq qspi controller has implemented this feature [1]
32   +------------+        CS             +---------------+
33   |            |---------------------->|               |
35   |            |            +=========>| memory        |
37   |            |            |    +---->|               |
38   | Controller |        CS  |    |     +---------------+
39   | SPI/QSPI   |------------|----|---->|               |
41   |            |<===========+====|====>| memory        |
43   |            |-----------------+---->|               |
44   +------------+                       +---------------+
46        - two memory flash devices should has same hw part attributes (like size,
48        - Configurations:
50                Enable U_PAGE[BIT:28] if U_PAGE flag set - upper memory
51                Disable U_PAGE[BIT:28] if U_PAGE flag unset - lower memory
52        - Operation:
54                by default, if U_PAGE is unset lower memory should accessible,
55                once user wants to access upper memory need to set U_PAGE.
58 	- dual spi/qspi flash memories are connected with a single chipselect
60 	- xilinx zynq qspi controller has implemented this feature [1]
62   +-------------+           CS		+---------------+
63   |		|---------------------->|		|
65   | 		|<=====================>| memory	|
67   |		|---------------------->|		|
68   | Controller	|	    CS		+---------------+
69   | SPI/QSPI	|---------------------->|		|
71   | 		|<=====================>| memory	|
73   |		|---------------------->|		|
74   +-------------+			+---------------+
76 	- two memory flash devices should has same hw part attributes (like size,
78 	- Configurations:
80 	- Operation:
81 		Even bits, i.e. bit 0, 2, 4 ., of a data word is located in the lower memory
82 		and odd bits, i.e. bit 1, 3, 5, ., of a data word is located in the upper memory.
84 Note: Technically there is only one CS line from the controller, but
85 zynq qspi controller has an internal hw logic to enable additional CS
86 when controller is configured for dual memories.
88 [1] http://www.xilinx.com/support/documentation/user_guides/ug585-Zynq-7000-TRM.pdf
90 --
92 05-01-2014.