Lines Matching refs:interleaving

1 Table of interleaving 2-4 controllers
25 Table of 2-way interleaving modes supported in cpu/8xxx/ddr/
49  interleaving using "2x2" rank interleaving, it only interleaves {CS0+CS1}
53  For memory controller interleaving, identical DIMMs are suggested. Software
56 The ways to configure the ddr interleaving mode
58 1. In board header file(e.g.MPC8572DS.h), add default interleaving setting
64 2. Run U-Boot "setenv" command to configure the memory interleaving mode.
67   # disable memory controller interleaving
70   # cacheline interleaving
73   # page interleaving
76   # bank interleaving
82   # 1KB 3-way interleaving
85   # 4KB 3-way interleaving
88   # 8KB 3-way interleaving
91   # disable bank (chip-select) interleaving
94   # bank(chip-select) interleaving cs0+cs1
97   # bank(chip-select) interleaving cs2+cs3
100   # bank(chip-select) interleaving (cs0+cs1) and (cs2+cs3)  (2x2)
103   # bank(chip-select) interleaving (cs0+cs1+cs2+cs3) (4x1)
106   # bank(chip-select) interleaving (auto)