Lines Matching refs:hwconfig
61 "hwconfig=fsl_ddr:ctlr_intlv=bank" \
68 setenv hwconfig "fsl_ddr:ctlr_intlv=null"
71 setenv hwconfig "fsl_ddr:ctlr_intlv=cacheline"
74 setenv hwconfig "fsl_ddr:ctlr_intlv=page"
77 setenv hwconfig "fsl_ddr:ctlr_intlv=bank"
80 setenv hwconfig "fsl_ddr:ctlr_intlv=superbank"
83 setenv hwconfig "fsl_ddr:ctlr_intlv=3way_1KB"
86 setenv hwconfig "fsl_ddr:ctlr_intlv=3way_4KB"
89 setenv hwconfig "fsl_ddr:ctlr_intlv=3way_8KB"
92 setenv hwconfig "fsl_ddr:bank_intlv=null"
95 setenv hwconfig "fsl_ddr:bank_intlv=cs0_cs1"
98 setenv hwconfig "fsl_ddr:bank_intlv=cs2_cs3"
101 setenv hwconfig "fsl_ddr:bank_intlv=cs0_cs1_and_cs2_cs3"
104 setenv hwconfig "fsl_ddr:bank_intlv=cs0_cs1_cs2_cs3"
107 setenv hwconfig "fsl_ddr:bank_intlv=auto"
113 If the DDR controller supports address hashing, it can be enabled by hwconfig.
116 hwconfig=fsl_ddr:addr_hash=true
121 ECC can be turned on/off by hwconfig.
124 hwconfig=fsl_ddr:ecc=off
129 address parity can be turned on/off by hwconfig.
131 hwconfig=fsl_ddr:parity=on
147 Combination of hwconfig
152 hwconfig=fsl_ddr:addr_hash=true,ctlr_intlv=cacheline,bank_intlv=cs0_cs1_cs2_cs3,ecc=on