u-boot/doc/README.POST

1 Power-On-Self-Test support in U-Boot
2 ------------------------------------
4 This project is to support Power-On-Self-Test (POST) in U-Boot.
6 1. High-level requirements
11    and running Power-On-Self-Test in U-Boot. This framework shall
21       The framework shall allow run-time configuration of the lists
22       of tests running on normal/power-fail booting.
31 3) The following POST tests shall be developed for MPC823E-based
51 enhancing U-Boot/Linux to provide a common framework for running POST
54 2.1. Hardware-independent POST layer
56 A new optional module will be added to U-Boot, which will run POST
57 tests and collect their results at boot time. Also, U-Boot will
61 The list of available POST tests will be configured at U-Boot build
65   1) Tests running on power-on booting only
68      power-on reset (e.g. watchdog test)
70   2) Tests running on normal booting only
75   3) Tests running in special "slow test mode" only
85 For example, SDRAM test may run in both normal and "slow test" mode.
86 In normal mode, SDRAM test may perform a fast superficial memory test
87 only, while running in slow test mode it may perform a full memory
88 check-up.
113 rest of U-Boot.
117 #define POST_POWERON		0x01	/* test runs on power-on booting */
118 #define POST_NORMAL		0x02	/* test runs on normal booting */
138      mode the test is executed in (power-on, normal, power-fail,
159 Also, the following board-specific routines will be called from the
160 U-Boot common code:
164      This routine will return the mode the system is running in
170      will be called on power-fail booting after running all POST
177      power-on long-running tests shall be executed or not ("normal"
178      versus "slow" test mode).
181 filled at U-Boot build time. The format of entry in this array will
212      above, which will specify the mode the test is running in
213      (power-on, normal, power-fail or manual mode), the moment it
223      mode the test is running in (POST_POWERON, POST_NORMAL,
229 The lists of the POST tests that should be run at power-on/normal/
230 power-fail booting will be kept in the environment. Namely, the
240 --------------------------------------------
242 <test-specific output>
244 --------------------------------------------
249 save it in non-volatile RAM (NVRAM), transfer it to a dedicated
254 All POST-related code will be #ifdef'ed with the CONFIG_POST macro.
262 		"On-board peripherals test", "board", \
263 		"  This test performs full check-up of the " \
264 		"on-board hardware.", \
282 A new subdirectory will be created in the U-Boot root directory. It
293 user-space library will be developed to provide the POST interface
298 A new command, diag, will be added to U-Boot. This command will be
307   cache             - cache test
308   cpu               - CPU test
309   enet              - SCC/FCC ethernet test
318 cpu - CPU test
320 cache - cache test
338 handler of the power-fail IRQ on booting. Being called, the handler
344 The POST layer of U-Boot will check whether the system runs in
345 power-fail mode. If it does, the system will be powered off after
388 		/* 10-second delay */
397 2.2. Hardware-specific details
399 This project will also develop a set of POST tests for MPC8xx- based
410      test will take several milliseconds and will run on normal
416      run on normal booting.
421      will always run on booting. On normal booting, only a limited
422      amount of RAM will be checked. On power-fail booting a fool
423      memory check-up will be performed.
436      a general-purpose register (mfcr) and comparing this value with
440      general-purpose register (mfcr) and comparing the value of this
444      4-bit condition fields, moving the value of the conditional
445      register to a general-purpose register (mfcr) and comparing it
455      the test will contain a pre-built table containing the
466      The test will contain a pre-built table of instructions,
474      general-purpose registers.
502      such combinations will be pre-built and linked in U-Boot at
510      All operations will be performed on a 16-byte array. The array
511      will be 4-byte aligned. The base register will point to offset
512      8. The immediate offset (index register) will range in [-8 ...
514      alignment exceptions. The test will contain a pre-built table
531 The CPU test will run in RAM in order to allow run-time modification
534 2.2.1.2 Special-Purpose Registers Tests
545     - turn on the data cache
546     - switch the data cache to write-back or write-through mode
547     - invalidate the data cache
548     - write the negative pattern to a cached area
549     - read the area
555     - turn on the data cache
556     - switch the data cache to write-back or write-through mode
557     - invalidate the data cache
558     - write the zero pattern to a cached area
559     - turn off the data cache
560     - write the negative pattern to the area
561     - turn on the data cache
562     - read the area
566   3) Write-through mode test
568     - turn on the data cache
569     - switch the data cache to write-through mode
570     - invalidate the data cache
571     - write the zero pattern to a cached area
572     - flush the data cache
573     - write the negative pattern to the area
574     - turn off the data cache
575     - read the area
579   4) Write-back mode test
581     - turn on the data cache
582     - switch the data cache to write-back mode
583     - invalidate the data cache
584     - write the negative pattern to a cached area
585     - flush the data cache
586     - write the zero pattern to the area
587     - invalidate the data cache
588     - read the area
597     - turn on the instruction cache
598     - unlock the entire instruction cache
599     - invalidate the instruction cache
600     - lock a branch instruction in the instruction cache
601     - replace the branch instruction with "nop"
602     - jump to the branch instruction
603     - check that the branch instruction was executed
607     - turn on the instruction cache
608     - unlock the entire instruction cache
609     - invalidate the instruction cache
610     - jump to a branch instruction
611     - check that the branch instruction was executed
612     - replace the branch instruction with "nop"
613     - invalidate the instruction cache
614     - jump to the branch instruction
615     - check that the "nop" instruction was executed
617 The CPU test will run in RAM in order to allow run-time modification
632  4) bit-flip pattern ((1 << (offset % 32)), ~(1 << (offset % 32)))
638 to detect far-located errors, i.e. situations when writing to one
643 Being run in normal mode, the test will verify only small 4Kb regions
645 following areas will be verified: 0x00000000-0x00000800,
646 0x000ff800-0x00100800, 0x001ff800-0x00200800, ..., 0x03fff800-
647 0x04000000. If the test is run in power-fail mode, it will verify the
650 The memory test will run in ROM before relocating U-Boot to RAM in
656 peculiarities and use common U-Boot interfaces only. These tests do
681 test routine will make a 10-second delay. If the system does not
696      period of time (5-10 seconds).
702      will be performed for both leap- and nonleap-years.
716 The internal (local) loopback mode will be used to test SCC. To do
727 To perform these tests the internal (local) loopback mode will be