xes/xpedite537x/ddr.c

23  *   1.) CPO (Read Capture Delay)
27  *   2.) WR_DATA_DELAY (Write Command to Data Strobe Delay)
32  *                   of 1/2 clock delay.
41  *     ====== XPedite5370 DDR2-600 read delay calculations ======
47  *     Minimum chip delay (Ch 0): 1.372ns
48  *     Maximum chip delay (Ch 0): 2.914ns
49  *     Minimum chip delay (Ch 1): 1.220ns
50  *     Maximum chip delay (Ch 1): 2.595ns
54  *     Minimum delay calc (Ch 0):
55  *     clock prop - dram skew + min dqs prop delay + clk_adjust + min chip dly
60  *     Maximum delay calc (Ch 0):
61  *     clock prop + dram skew + max dqs prop delay + clk_adjust + max chip dly
66  *     Minimum delay calc (Ch 1):
67  *     clock prop - dram skew + min dqs prop delay + clk_adjust + min chip dly
72  *     Maximum delay calc (Ch 1):
73  *     clock prop + dram skew + max dqs prop delay + clk_adjust + min chip dly
78  *     Ch.0: 3.808ns to 6.240ns additional delay needed  (pick 5ns as target)
80  *     Ch.1: 3.288ns to 5.536ns additional delay needed  (pick 4.4ns as target)
84  *     ====== XPedite5370 DDR2-800 read delay calculations ======
90  *     Minimum chip delay (Ch 0): 1.372ns
91  *     Maximum chip delay (Ch 0): 2.914ns
92  *     Minimum chip delay (Ch 1): 1.220ns
93  *     Maximum chip delay (Ch 1): 2.595ns
97  *     Minimum delay calc (Ch 0):
98  *     clock prop - dram skew + min dqs prop delay + clk_adjust + min chip dly
103  *     Maximum delay calc (Ch 0):
104  *     clock prop + dram skew + max dqs prop delay + clk_adjust + max chip dly
109  *     Minimum delay calc (Ch 1):
110  *     clock prop - dram skew + min dqs prop delay + clk_adjust + min chip dly
115  *     Maximum delay calc (Ch 1):
116  *     clock prop + dram skew + max dqs prop delay + clk_adjust + min chip dly
121  *     Ch.0: 3.341ns to 5.673ns additional delay needed  (pick 4.5ns as target)
123  *     Ch.1: 2.822ns to 4.968ns additional delay needed  (pick 3.9ns as target)
144  *      period at DDR2-600 or DDR2-800, so no additional delay is needed over
147  *      See Figure 9-53 in MPC8572E manual: "1/2 delay" in Freescale's
148  *      terminology corresponds to exactly one clock period delay after
149  *      the CAS strobe. (due to the fact that the "delay" is referenced