Lines Matching +full:clock +full:- +full:delay
5 * SPDX-License-Identifier: GPL-2.0+
21 * There are four board-specific SDRAM timing parameters which must be
23 * 1.) CPO (Read Capture Delay)
24 * - TIMING_CFG_2 register
26 * chip-specific internal delays.
27 * 2.) WR_DATA_DELAY (Write Command to Data Strobe Delay)
28 * - TIMING_CFG_2 register
30 * Unless clock and DQ lanes are very different
32 * of 1/2 clock delay.
33 * 3.) CLK_ADJUST (Clock and Addr/Cmd alignment control)
34 * - DDR_SDRAM_CLK_CNTL register
37 * - TIMING_CFG_2 register
39 * Usually only needed with heavy load/very high speed (>DDR2-800)
41 * ====== XPedite5370 DDR2-600 read delay calculations ======
44 * contains the chip-specific delays for 8548E, 8572, etc.
47 * Minimum chip delay (Ch 0): 1.372ns
48 * Maximum chip delay (Ch 0): 2.914ns
49 * Minimum chip delay (Ch 1): 1.220ns
50 * Maximum chip delay (Ch 1): 2.595ns
54 * Minimum delay calc (Ch 0):
55 * clock prop - dram skew + min dqs prop delay + clk_adjust + min chip dly
56 * 2.3" * 180 - 400ps + 1.9" * 180 + 2080ps + 1372ps
60 * Maximum delay calc (Ch 0):
61 * clock prop + dram skew + max dqs prop delay + clk_adjust + max chip dly
66 * Minimum delay calc (Ch 1):
67 * clock prop - dram skew + min dqs prop delay + clk_adjust + min chip dly
68 * 1.46" * 180- 400ps + 0.7" * 180 + 2080ps + 1220ps
72 * Maximum delay calc (Ch 1):
73 * clock prop + dram skew + max dqs prop delay + clk_adjust + min chip dly
78 * Ch.0: 3.808ns to 6.240ns additional delay needed (pick 5ns as target)
79 * This is 1.5 clock cycles, pick CPO = READ_LAT + 3/2 (0x8)
80 * Ch.1: 3.288ns to 5.536ns additional delay needed (pick 4.4ns as target)
81 * This is 1.32 clock cycles, pick CPO = READ_LAT + 5/4 (0x7)
84 * ====== XPedite5370 DDR2-800 read delay calculations ======
87 * contains the chip-specific delays for 8548E, 8572, etc.
90 * Minimum chip delay (Ch 0): 1.372ns
91 * Maximum chip delay (Ch 0): 2.914ns
92 * Minimum chip delay (Ch 1): 1.220ns
93 * Maximum chip delay (Ch 1): 2.595ns
97 * Minimum delay calc (Ch 0):
98 * clock prop - dram skew + min dqs prop delay + clk_adjust + min chip dly
99 * 2.3" * 180 - 350ps + 1.9" * 180 + 1563ps + 1372ps
103 * Maximum delay calc (Ch 0):
104 * clock prop + dram skew + max dqs prop delay + clk_adjust + max chip dly
109 * Minimum delay calc (Ch 1):
110 * clock prop - dram skew + min dqs prop delay + clk_adjust + min chip dly
111 * 1.46" * 180- 350ps + 0.7" * 180 + 1563ps + 1220ps
115 * Maximum delay calc (Ch 1):
116 * clock prop + dram skew + max dqs prop delay + clk_adjust + min chip dly
121 * Ch.0: 3.341ns to 5.673ns additional delay needed (pick 4.5ns as target)
122 * This is 1.8 clock cycles, pick CPO = READ_LAT + 7/4 (0x9)
123 * Ch.1: 2.822ns to 4.968ns additional delay needed (pick 3.9ns as target)
124 * This is 1.56 clock cycles, pick CPO = READ_LAT + 3/2 (0x8)
129 * 75% of an SDRAM clock period—and no later than 125% of a clock
130 * period—from the capturing clock edge of the command/address at the
143 * Both of these values are much less than 25% of the clock
144 * period at DDR2-600 or DDR2-800, so no additional delay is needed over
147 * See Figure 9-53 in MPC8572E manual: "1/2 delay" in Freescale's
148 * terminology corresponds to exactly one clock period delay after
149 * the CAS strobe. (due to the fact that the "delay" is referenced
223 popts->clk_adjust = bopts[i].clk_adjust; in fsl_ddr_board_options()
224 popts->cpo_override = bopts[i].cpo_override; in fsl_ddr_board_options()
225 popts->write_data_delay = bopts[i].write_data_delay; in fsl_ddr_board_options()
230 * Factors to consider for half-strength driver enable: in fsl_ddr_board_options()
231 * - number of DIMMs installed in fsl_ddr_board_options()
233 popts->half_strength_driver_enable = 0; in fsl_ddr_board_options()