Lines Matching +full:2 +full:ns
16 i2c_read(i2c_address, SPD_EEPROM_OFFSET, 2, (uchar *)spd, in get_spd()
27 * 2.) WR_DATA_DELAY (Write Command to Data Strobe Delay)
31 * lengths (>2"), this should be set to the nominal value
32 * of 1/2 clock delay.
36 * 4.) 2T Timing on Addr/Ctl
47 * Minimum chip delay (Ch 0): 1.372ns
48 * Maximum chip delay (Ch 0): 2.914ns
49 * Minimum chip delay (Ch 1): 1.220ns
50 * Maximum chip delay (Ch 1): 2.595ns
52 * CLK adjust = 5 (from simulations) = 5/8* 3.33ns = 2080ps
58 * = 3.808ns
64 * = 6.240ns
70 * = 3.288ns
76 * = 5.536ns
78 * Ch.0: 3.808ns to 6.240ns additional delay needed (pick 5ns as target)
79 * This is 1.5 clock cycles, pick CPO = READ_LAT + 3/2 (0x8)
80 * Ch.1: 3.288ns to 5.536ns additional delay needed (pick 4.4ns as target)
90 * Minimum chip delay (Ch 0): 1.372ns
91 * Maximum chip delay (Ch 0): 2.914ns
92 * Minimum chip delay (Ch 1): 1.220ns
93 * Maximum chip delay (Ch 1): 2.595ns
95 * CLK adjust = 5 (from simulations) = 5/8* 2.5ns = 1563ps
101 * = 3.341ns
107 * = 5.673ns
113 * = 2.822ns
119 * = 4.968ns
121 * Ch.0: 3.341ns to 5.673ns additional delay needed (pick 4.5ns as target)
123 * Ch.1: 2.822ns to 4.968ns additional delay needed (pick 3.9ns as target)
124 * This is 1.56 clock cycles, pick CPO = READ_LAT + 3/2 (0x8)
134 * Ch. 0 8572 to DRAM propagation (DQ lanes) : 1.9" * 180 = 0.342ns
135 * Ch. 0 8572 to DRAM propagation (CLKs) : 2.3" * 180 = 0.414ns
136 * Ch. 1 8572 to DRAM propagation (DQ lanes) : 0.7" * 180 = 0.126ns
137 * Ch. 1 8572 to DRAM propagation (CLKs ) : 1.47" * 180 = 0.264ns
140 * Ch. 0 0.072ns
141 * Ch. 1 0.138ns
145 * the 1/2 cycle which normally aligns the first DQS transition
147 * See Figure 9-53 in MPC8572E manual: "1/2 delay" in Freescale's
162 static struct board_memctl_options bopts_ctrl[][2] = {
171 .write_data_delay = 2,
179 .write_data_delay = 2,
190 .write_data_delay = 2,
198 .write_data_delay = 2,