Lines Matching +full:0 +full:x00010001

31  *   0x30 == 40 Ohm
32  *   0x28 == 48 Ohm
34 #define IMX6DQ_DRIVE_STRENGTH		0x30
35 #define IMX6SDL_DRIVE_STRENGTH	0x28
46 	.dram_sdba2 = 0x00000000,
69 	.grp_ddr_type = 0x000c0000,
70 	.grp_ddrmode_ctl = 0x00020000,
71 	.grp_ddrpke = 0x00000000,
74 	.grp_ddrmode = 0x00020000,
94 	.dram_sdba2 = 0x00000000,
117 	.grp_ddr_type = 0x000c0000,
118 	.grp_ddrmode_ctl = 0x00020000,
119 	.grp_ddrpke = 0x00000000,
122 	.grp_ddrmode = 0x00020000,
146 	.SRT = 0,
150 	.p0_mpwldectrl0 = 0x00350035,
151 	.p0_mpwldectrl1 = 0x001F001F,
152 	.p1_mpwldectrl0 = 0x00010001,
153 	.p1_mpwldectrl1 = 0x00010001,
154 	.p0_mpdgctrl0 = 0x43510360,
155 	.p0_mpdgctrl1 = 0x0342033F,
156 	.p1_mpdgctrl0 = 0x033F033F,
157 	.p1_mpdgctrl1 = 0x03290266,
158 	.p0_mprddlctl = 0x4B3E4141,
159 	.p1_mprddlctl = 0x47413B4A,
160 	.p0_mpwrdlctl = 0x42404843,
161 	.p1_mpwrdlctl = 0x4C3F4C45,
165 	.p0_mpwldectrl0 = 0x002F0038,
166 	.p0_mpwldectrl1 = 0x001F001F,
167 	.p1_mpwldectrl0 = 0x001F001F,
168 	.p1_mpwldectrl1 = 0x001F001F,
169 	.p0_mpdgctrl0 = 0x425C0251,
170 	.p0_mpdgctrl1 = 0x021B021E,
171 	.p1_mpdgctrl0 = 0x021B021E,
172 	.p1_mpdgctrl1 = 0x01730200,
173 	.p0_mprddlctl = 0x45474C45,
174 	.p1_mprddlctl = 0x44464744,
175 	.p0_mpwrdlctl = 0x3F3F3336,
176 	.p1_mpwrdlctl = 0x32383630,
182 	.cs1_mirror = 0,
192 	.walat = 0,
194 	.rst_to_cke = 0x23,
195 	.sde_to_rst = 0x10,
205 	writel(0x00C03F3F, &ccm->CCGR0);  in ccgr_init()
206 	writel(0x0030FC03, &ccm->CCGR1);  in ccgr_init()
207 	writel(0x0FFFC000, &ccm->CCGR2);  in ccgr_init()
208 	writel(0x3FF00000, &ccm->CCGR3);  in ccgr_init()
209 	writel(0x00FFF300, &ccm->CCGR4);  in ccgr_init()
210 	writel(0x0F0000C3, &ccm->CCGR5);  in ccgr_init()
211 	writel(0x000003FF, &ccm->CCGR6);  in ccgr_init()
257 	memset(__bss_start, 0, __bss_end - __bss_start);  in board_init_f()
260 	board_init_r(NULL, 0);  in board_init_f()