Lines Matching +full:0 +full:x00000028
79 return 0; in dram_init()
89 .gp = IMX_GPIO_NR(1, 0),
117 printf("PMIC: PFUZE3000 DEV_ID=0x%x REV_ID=0x%x\n", reg, rev_id); in power_init_board()
121 reg |= 0x1; in power_init_board()
126 ret = pmic_reg_write(p, PFUZE3000_SW1AMODE, 0xc); in power_init_board()
130 ret = pmic_reg_write(p, PFUZE3000_SW1BMODE, 0xc); in power_init_board()
134 ret = pmic_reg_write(p, PFUZE3000_SW2MODE, 0xc); in power_init_board()
138 ret = pmic_reg_write(p, PFUZE3000_SW3MODE, 0xc); in power_init_board()
144 reg &= ~0x3f; in power_init_board()
152 reg &= ~0x3f; in power_init_board()
160 reg &= ~0xc0; in power_init_board()
161 reg |= 0x40; in power_init_board()
168 reg &= ~0xc0; in power_init_board()
169 reg |= 0x40; in power_init_board()
176 reg &= ~0x3f; in power_init_board()
184 reg &= ~0x3f; in power_init_board()
192 reg &= ~0x0f; in power_init_board()
200 reg &= ~0x0f; in power_init_board()
203 reg |= 0x10; in power_init_board()
208 return 0; in power_init_board()
280 gpio_direction_output(IMX_GPIO_NR(2, 1) , 0); in setup_fec()
307 phydev = phy_find_by_mask(bus, (0x1 << CONFIG_FEC_MXC_PHYADDR), in board_eth_init()
320 return 0; in board_eth_init()
328 return 0; in board_phy_config()
334 gd->bd->bi_boot_params = PHYS_SDRAM + 0x100; in board_init()
353 setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1); in board_init()
356 return 0; in board_init()
367 gpio_direction_input(IMX_GPIO_NR(4, 0)); in get_board_value()
370 r185 = gpio_get_value(IMX_GPIO_NR(4, 0)); in get_board_value()
376 * Basic 0 0 in get_board_value()
377 * Basic Ks 0 1 in get_board_value()
378 * Full 1 0 in get_board_value()
389 return 0; in board_early_init_f()
393 {USDHC2_BASE_ADDR, 0, 4},
407 usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK); in board_mmc_init()
408 usdhc_cfg[0].esdhc_base = USDHC2_BASE_ADDR; in board_mmc_init()
412 gd->arch.sdhc_clk = usdhc_cfg[0].sdhc_clk; in board_mmc_init()
413 return fsl_esdhc_initialize(bis, &usdhc_cfg[0]); in board_mmc_init()
434 return 0; in checkboard()
443 return 0; in board_late_init()
452 .dram_dqm0 = 0x00000028,
453 .dram_dqm1 = 0x00000028,
454 .dram_dqm2 = 0x00000028,
455 .dram_dqm3 = 0x00000028,
456 .dram_ras = 0x00000020,
457 .dram_cas = 0x00000020,
458 .dram_odt0 = 0x00000020,
459 .dram_odt1 = 0x00000020,
460 .dram_sdba2 = 0x00000000,
461 .dram_sdcke0 = 0x00003000,
462 .dram_sdcke1 = 0x00003000,
463 .dram_sdclk_0 = 0x00000030,
464 .dram_sdqs0 = 0x00000028,
465 .dram_sdqs1 = 0x00000028,
466 .dram_sdqs2 = 0x00000028,
467 .dram_sdqs3 = 0x00000028,
468 .dram_reset = 0x00000020,
472 .grp_addds = 0x00000020,
473 .grp_ddrmode_ctl = 0x00020000,
474 .grp_ddrpke = 0x00000000,
475 .grp_ddrmode = 0x00020000,
476 .grp_b0ds = 0x00000028,
477 .grp_b1ds = 0x00000028,
478 .grp_ctlds = 0x00000020,
479 .grp_ddr_type = 0x000c0000,
480 .grp_b2ds = 0x00000028,
481 .grp_b3ds = 0x00000028,
485 .p0_mpwldectrl0 = 0x000E000B,
486 .p0_mpwldectrl1 = 0x000E0010,
487 .p0_mpdgctrl0 = 0x41600158,
488 .p0_mpdgctrl1 = 0x01500140,
489 .p0_mprddlctl = 0x3A383E3E,
490 .p0_mpwrdlctl = 0x3A383C38,
494 .p0_mpwldectrl0 = 0x001E0022,
495 .p0_mpwldectrl1 = 0x001C0019,
496 .p0_mpdgctrl0 = 0x41540150,
497 .p0_mpdgctrl1 = 0x01440138,
498 .p0_mprddlctl = 0x403E4644,
499 .p0_mpwrdlctl = 0x3C3A4038,
534 writel(0xFFFFFFFF, &ccm->CCGR0); in ccgr_init()
535 writel(0xFFFFFFFF, &ccm->CCGR1); in ccgr_init()
536 writel(0xFFFFFFFF, &ccm->CCGR2); in ccgr_init()
537 writel(0xFFFFFFFF, &ccm->CCGR3); in ccgr_init()
538 writel(0xFFFFFFFF, &ccm->CCGR4); in ccgr_init()
539 writel(0xFFFFFFFF, &ccm->CCGR5); in ccgr_init()
540 writel(0xFFFFFFFF, &ccm->CCGR6); in ccgr_init()
541 writel(0xFFFFFFFF, &ccm->CCGR7); in ccgr_init()
552 .cs1_mirror = 0, in spl_dram_init()
559 .sde_to_rst = 0x10, /* 14 cycles, 200us (JEDEC default) */ in spl_dram_init()
560 .rst_to_cke = 0x23, /* 33 cycles, 500us (JEDEC default) */ in spl_dram_init()
590 memset(__bss_start, 0, __bss_end - __bss_start); in board_init_f()
593 board_init_r(NULL, 0); in board_init_f()