ti/dra7xx/evm.c

313 	.mpu.efuse.reg[OPP_NOM]	= STD_FUSE_OPP_VMIN_MPU_NOM,
314 	.mpu.efuse.reg_bits	= DRA752_EFUSE_REGBITS,
322 	.eve.efuse.reg[OPP_NOM]	= STD_FUSE_OPP_VMIN_DSPEVE_NOM,
323 	.eve.efuse.reg[OPP_OD]	= STD_FUSE_OPP_VMIN_DSPEVE_OD,
324 	.eve.efuse.reg[OPP_HIGH]	= STD_FUSE_OPP_VMIN_DSPEVE_HIGH,
325 	.eve.efuse.reg_bits	= DRA752_EFUSE_REGBITS,
333 	.gpu.efuse.reg[OPP_NOM]	= STD_FUSE_OPP_VMIN_GPU_NOM,
334 	.gpu.efuse.reg[OPP_OD]	= STD_FUSE_OPP_VMIN_GPU_OD,
335 	.gpu.efuse.reg[OPP_HIGH]	= STD_FUSE_OPP_VMIN_GPU_HIGH,
336 	.gpu.efuse.reg_bits	= DRA752_EFUSE_REGBITS,
342 	.core.efuse.reg[OPP_NOM]	= STD_FUSE_OPP_VMIN_CORE_NOM,
343 	.core.efuse.reg_bits = DRA752_EFUSE_REGBITS,
350 	.iva.efuse.reg[OPP_NOM]	= STD_FUSE_OPP_VMIN_IVA_NOM,
351 	.iva.efuse.reg[OPP_OD]	= STD_FUSE_OPP_VMIN_IVA_OD,
352 	.iva.efuse.reg[OPP_HIGH]	= STD_FUSE_OPP_VMIN_IVA_HIGH,
353 	.iva.efuse.reg_bits	= DRA752_EFUSE_REGBITS,
361 	.mpu.efuse.reg[OPP_NOM]	= STD_FUSE_OPP_VMIN_MPU_NOM,
362 	.mpu.efuse.reg_bits = DRA752_EFUSE_REGBITS,
368 	.core.efuse.reg[OPP_NOM]	= STD_FUSE_OPP_VMIN_CORE_NOM,
369 	.core.efuse.reg_bits = DRA752_EFUSE_REGBITS,
380 	.gpu.efuse.reg[OPP_NOM]	= STD_FUSE_OPP_VMIN_GPU_NOM,
381 	.gpu.efuse.reg[OPP_OD]	= STD_FUSE_OPP_VMIN_GPU_OD,
382 	.gpu.efuse.reg[OPP_HIGH]	= STD_FUSE_OPP_VMIN_GPU_HIGH,
383 	.gpu.efuse.reg_bits = DRA752_EFUSE_REGBITS,
391 	.eve.efuse.reg[OPP_NOM]	= STD_FUSE_OPP_VMIN_DSPEVE_NOM,
392 	.eve.efuse.reg[OPP_OD]	= STD_FUSE_OPP_VMIN_DSPEVE_OD,
393 	.eve.efuse.reg[OPP_HIGH]	= STD_FUSE_OPP_VMIN_DSPEVE_HIGH,
394 	.eve.efuse.reg_bits = DRA752_EFUSE_REGBITS,
402 	.iva.efuse.reg[OPP_NOM]	= STD_FUSE_OPP_VMIN_IVA_NOM,
403 	.iva.efuse.reg[OPP_OD]	= STD_FUSE_OPP_VMIN_IVA_OD,
404 	.iva.efuse.reg[OPP_HIGH]	= STD_FUSE_OPP_VMIN_IVA_HIGH,
405 	.iva.efuse.reg_bits = DRA752_EFUSE_REGBITS,
417 	.mpu.efuse.reg[OPP_NOM]	= STD_FUSE_OPP_VMIN_MPU_NOM,
418 	.mpu.efuse.reg_bits	= DRA752_EFUSE_REGBITS,
424 	.core.efuse.reg[OPP_NOM]	= STD_FUSE_OPP_VMIN_CORE_NOM,
425 	.core.efuse.reg_bits = DRA752_EFUSE_REGBITS,
430 	.gpu.efuse.reg[OPP_NOM]	= STD_FUSE_OPP_VMIN_GPU_NOM,
431 	.gpu.efuse.reg_bits = DRA752_EFUSE_REGBITS,
442 	.eve.efuse.reg[OPP_NOM]	= STD_FUSE_OPP_VMIN_DSPEVE_NOM,
443 	.eve.efuse.reg[OPP_HIGH] = STD_FUSE_OPP_VMIN_DSPEVE_HIGH,
444 	.eve.efuse.reg_bits = DRA752_EFUSE_REGBITS,
451 	.iva.efuse.reg[OPP_NOM]	= STD_FUSE_OPP_VMIN_IVA_NOM,
452 	.iva.efuse.reg[OPP_HIGH] = STD_FUSE_OPP_VMIN_IVA_HIGH,
453 	.iva.efuse.reg_bits = DRA752_EFUSE_REGBITS,
886 	/* try reading mac address from efuse */  in board_eth_init()