Lines Matching refs:M1
111 MUX_VAL(CP(GPMC_NCS6), (IEN | PTD | DIS | M1)) /*SYS_nDMA_REQ2*/\
112 MUX_VAL(CP(GPMC_NCS7), (IEN | PTU | EN | M1)) /*SYS_nDMA_REQ3*/\
206 MUX_VAL(CP(MCBSP3_DX), (IEN | PTD | DIS | M1)) /*UART2_CTS*/\
207 MUX_VAL(CP(MCBSP3_DR), (IDIS | PTD | DIS | M1)) /*UART2_RTS*/\
208 MUX_VAL(CP(MCBSP3_CLKX), (IDIS | PTD | DIS | M1)) /*UART2_TX*/\
209 MUX_VAL(CP(MCBSP3_FSX), (IEN | PTD | DIS | M1)) /*UART2_RX*/\
219 MUX_VAL(CP(MCBSP4_CLKX), (IEN | PTD | DIS | M1)) /*SSI1_DAT_RX*/\
220 MUX_VAL(CP(MCBSP4_DR), (IEN | PTD | DIS | M1)) /*SSI1_FLAG_RX*/\
221 MUX_VAL(CP(MCBSP4_DX), (IEN | PTD | DIS | M1)) /*SSI1_RDY_RX*/\
222 MUX_VAL(CP(MCBSP4_FSX), (IEN | PTD | DIS | M1)) /*SSI1_WAKE*/\
413 MUX_VAL(CP(MMC2_DAT4), (IEN | PTU | EN | M1)) /*MMC2_DIR_DAT0*/\
414 MUX_VAL(CP(MMC2_DAT5), (IEN | PTU | EN | M1)) /*MMC2_DIR_DAT1*/\
415 MUX_VAL(CP(MMC2_DAT6), (IEN | PTU | EN | M1)) /*MMC2_DIR_CMD*/\
416 MUX_VAL(CP(MMC2_DAT7), (IEN | PTU | EN | M1)) /*MMC2_CLKIN*/\
417 MUX_VAL(CP(MCBSP1_CLKR), (IEN | PTU | EN | M1)) /*MCSPI4_CLK*/\
419 MUX_VAL(CP(MCBSP1_DX), (IEN | PTD | EN | M1)) /*MCSPI4_SIMO*/\
420 MUX_VAL(CP(MCBSP1_DR), (IEN | PTD | DIS | M1)) /*MCSPI4_SOMI*/\
421 MUX_VAL(CP(MCBSP1_FSX), (IEN | PTD | EN | M1)) /*MCSPI4_CS0*/\
443 MUX_VAL(CP(MCBSP1_CLKR), (IEN | PTU | DIS | M1)) /*MCSPI4_CLK*/\
444 MUX_VAL(CP(MCBSP1_DX), (IDIS | PTU | DIS | M1)) /*MCSPI4_SIMO*/\
445 MUX_VAL(CP(MCBSP1_DR), (IEN | PTU | EN | M1)) /*MCSPI4_SOMI*/\
446 MUX_VAL(CP(MCBSP1_FSX), (IDIS | PTU | DIS | M1)) /*MCSPI4_CS0*/