11 	int pin;  in eth_init_board()  local
17 	setbits_le32(&ccm->ahb_reset0_cfg, 0x1 << AHB_RESET_OFFSET_GMAC);  in eth_init_board()
18 	setbits_le32(&ccm->ahb_gate0, 0x1 << AHB_GATE_OFFSET_GMAC);  in eth_init_board()
20 	setbits_le32(&ccm->ahb_gate1, 0x1 << AHB_GATE_OFFSET_GMAC);  in eth_init_board()
25 	setbits_le32(&ccm->gmac_clk_cfg, CCM_GMAC_CTRL_TX_CLK_SRC_INT_RGMII |  in eth_init_board()
27 	setbits_le32(&ccm->gmac_clk_cfg,  in eth_init_board()
30 	setbits_le32(&ccm->gmac_clk_cfg, CCM_GMAC_CTRL_TX_CLK_SRC_MII |  in eth_init_board()
35 	/* Configure pin mux settings for GMAC */  in eth_init_board()
36 	for (pin = SUNXI_GPA(0); pin <= SUNXI_GPA(16); pin++) {  in eth_init_board()
39 		if (pin == SUNXI_GPA(9) || pin == SUNXI_GPA(14))  in eth_init_board()
42 		sunxi_gpio_set_cfgpin(pin, SUN7I_GPA_GMAC);  in eth_init_board()
43 		sunxi_gpio_set_drv(pin, 3);  in eth_init_board()
46 	/* Configure sun6i RGMII mode pin mux settings */  in eth_init_board()
47 	for (pin = SUNXI_GPA(0); pin <= SUNXI_GPA(3); pin++) {  in eth_init_board()
48 		sunxi_gpio_set_cfgpin(pin, SUN6I_GPA_GMAC);  in eth_init_board()
49 		sunxi_gpio_set_drv(pin, 3);  in eth_init_board()
51 	for (pin = SUNXI_GPA(9); pin <= SUNXI_GPA(14); pin++) {  in eth_init_board()
52 		sunxi_gpio_set_cfgpin(pin, SUN6I_GPA_GMAC);  in eth_init_board()
53 		sunxi_gpio_set_drv(pin, 3);  in eth_init_board()
55 	for (pin = SUNXI_GPA(19); pin <= SUNXI_GPA(20); pin++) {  in eth_init_board()
56 		sunxi_gpio_set_cfgpin(pin, SUN6I_GPA_GMAC);  in eth_init_board()
57 		sunxi_gpio_set_drv(pin, 3);  in eth_init_board()
59 	for (pin = SUNXI_GPA(25); pin <= SUNXI_GPA(27); pin++) {  in eth_init_board()
60 		sunxi_gpio_set_cfgpin(pin, SUN6I_GPA_GMAC);  in eth_init_board()
61 		sunxi_gpio_set_drv(pin, 3);  in eth_init_board()
64 	/* Configure sun6i GMII mode pin mux settings */  in eth_init_board()
65 	for (pin = SUNXI_GPA(0); pin <= SUNXI_GPA(27); pin++) {  in eth_init_board()
66 		sunxi_gpio_set_cfgpin(pin, SUN6I_GPA_GMAC);  in eth_init_board()
67 		sunxi_gpio_set_drv(pin, 2);  in eth_init_board()
70 	/* Configure sun6i MII mode pin mux settings */  in eth_init_board()
71 	for (pin = SUNXI_GPA(0); pin <= SUNXI_GPA(3); pin++)  in eth_init_board()
72 		sunxi_gpio_set_cfgpin(pin, SUN6I_GPA_GMAC);  in eth_init_board()
73 	for (pin = SUNXI_GPA(8); pin <= SUNXI_GPA(9); pin++)  in eth_init_board()
74 		sunxi_gpio_set_cfgpin(pin, SUN6I_GPA_GMAC);  in eth_init_board()
75 	for (pin = SUNXI_GPA(11); pin <= SUNXI_GPA(14); pin++)  in eth_init_board()
76 		sunxi_gpio_set_cfgpin(pin, SUN6I_GPA_GMAC);  in eth_init_board()
77 	for (pin = SUNXI_GPA(19); pin <= SUNXI_GPA(24); pin++)  in eth_init_board()
78 		sunxi_gpio_set_cfgpin(pin, SUN6I_GPA_GMAC);  in eth_init_board()
79 	for (pin = SUNXI_GPA(26); pin <= SUNXI_GPA(27); pin++)  in eth_init_board()
80 		sunxi_gpio_set_cfgpin(pin, SUN6I_GPA_GMAC);  in eth_init_board()