12  * Ported to SolidRun microSOM by Rabeeh Khoury <rabeeh@solid-run.com>
14  * SPDX-License-Identifier:	GPL-2.0+
17 #include <asm/arch/clock.h>
18 #include <asm/arch/imx-regs.h>
20 #include <asm/arch/mx6-pins.h>
24 #include <asm/mach-imx/iomux-v3.h>
25 #include <asm/mach-imx/sata.h>
26 #include <asm/mach-imx/video.h>
37 #include <usb/ehci-ci.h>
63 	gd->ram_size = imx_ddr_size();  in dram_init()
82 	/* These pins are for sensing if it is a CuBox-i or a HummingBoard */
110 	gd->arch.sdhc_clk = usdhc_cfg[0].sdhc_clk;  in board_mmc_init()
122 	/* GPIO16 -> AR8035 25MHz */
130 	/* AR8035 CLK_25M --> ENET_REF_CLK (V22) */
154 	if (phydev->drv->config)  in board_phy_config()
155 		phydev->drv->config(phydev);  in board_phy_config()
174 	setbits_le32(&iomuxc_regs->gpr[1], IOMUXC_GPR1_ENET_CLK_SEL_MASK);  in board_eth_init()
178 	bus = fec_get_miibus(IMX_FEC_BASE, -1);  in board_eth_init()
180 		return -EINVAL;  in board_eth_init()
184 		ret = -EINVAL;  in board_eth_init()
188 	debug("using phy at address %d\n", phydev->addr);  in board_eth_init()
189 	ret = fec_probe(bis, -1, IMX_FEC_BASE, bus, phydev);  in board_eth_init()
210 		.bus	= -1,
245 	/* set video pll to 455MHz (24MHz * (37+11/12) / 2) */  in setup_display()
246 	setbits_le32(&ccm->analog_pll_video, BM_ANADIG_PLL_VIDEO_POWERDOWN);  in setup_display()
248 	reg = readl(&ccm->analog_pll_video);  in setup_display()
253 	writel(reg, &ccm->analog_pll_video);  in setup_display()
255 	writel(BF_ANADIG_PLL_VIDEO_NUM_A(11), &ccm->analog_pll_video_num);  in setup_display()
256 	writel(BF_ANADIG_PLL_VIDEO_DENOM_B(12), &ccm->analog_pll_video_denom);  in setup_display()
259 	writel(reg, &ccm->analog_pll_video);  in setup_display()
261 	while (timeout--)  in setup_display()
262 		if (readl(&ccm->analog_pll_video) & BM_ANADIG_PLL_VIDEO_LOCK)  in setup_display()
265 		printf("Warning: video pll lock timeout!\n");  in setup_display()
266 		return -ETIMEDOUT;  in setup_display()
269 	reg = readl(&ccm->analog_pll_video);  in setup_display()
272 	writel(reg, &ccm->analog_pll_video);  in setup_display()
275 	clrbits_le32(&ccm->CCGR3, MXC_CCM_CCGR3_LDB_DI0_MASK);  in setup_display()
277 	/* select video_pll clock / 7  for ipu1_di0_clk -> 65MHz pixclock */  in setup_display()
278 	reg = readl(&ccm->chsccdr);  in setup_display()
285 	writel(reg, &ccm->chsccdr);  in setup_display()
288 	setbits_le32(&ccm->CCGR3, MXC_CCM_CCGR3_LDB_DI0_MASK);  in setup_display()
331 	gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;  in board_init()
349 	 * Machine selection -  in is_hummingboard()
351 	 * -------------------------  in is_hummingboard()
352 	 * HB rev 3.x     x     0  in is_hummingboard()
354 	 * HB             1     1  in is_hummingboard()
370 		puts("Board: MX6 Cubox-i\n");  in checkboard()
393 #include <asm/arch/mx6-ddr.h>
575 	writel(0x00C03F3F, &ccm->CCGR0);  in ccgr_init()
576 	writel(0x0030FC03, &ccm->CCGR1);  in ccgr_init()
577 	writel(0x0FFFC000, &ccm->CCGR2);  in ccgr_init()
578 	writel(0x3FF00000, &ccm->CCGR3);  in ccgr_init()
579 	writel(0x00FFF300, &ccm->CCGR4);  in ccgr_init()
580 	writel(0x0F0000C3, &ccm->CCGR5);  in ccgr_init()
581 	writel(0x000003FF, &ccm->CCGR6);  in ccgr_init()
635 	/* UART clocks enabled and gd valid - init serial console */  in board_init_f()
645 	memset(__bss_start, 0, __bss_end - __bss_start);  in board_init_f()