54 	popts->half_strength_driver_enable = 0;  in fsl_ddr_board_options()
61  * SPD from 0x51 to 0x53.  So we try and read 0x53 1st, and
62  * if that fails, then fall back to reading at 0x51.
70 		ret = i2c_read(ALT_SPD_EEPROM_ADDRESS, 0, 1, (uchar *)spd,  in get_spd()
72 		if (ret == 0)  in get_spd()
73 			return;		/* Good data at 0x53 */  in get_spd()
74 		memset(spd, 0, sizeof(generic_spd_eeprom_t));  in get_spd()
77 	ret = i2c_read(i2c_address, 0, 1, (uchar *)spd,  in get_spd()
81 		memset(spd, 0, sizeof(generic_spd_eeprom_t));  in get_spd()
95 	out_be32(&ddr->cs0_bnds,	0x0000007f);  in fixed_sdram()
96 	out_be32(&ddr->cs1_bnds,	0x008000ff);  in fixed_sdram()
97 	out_be32(&ddr->cs2_bnds,	0x00000000);  in fixed_sdram()
98 	out_be32(&ddr->cs3_bnds,	0x00000000);  in fixed_sdram()
100 	out_be32(&ddr->cs0_config,	0x80010101);  in fixed_sdram()
101 	out_be32(&ddr->cs1_config,	0x80010101);  in fixed_sdram()
102 	out_be32(&ddr->cs2_config,	0x00000000);  in fixed_sdram()
103 	out_be32(&ddr->cs3_config,	0x00000000);  in fixed_sdram()
105 	out_be32(&ddr->timing_cfg_3,	0x00000000);  in fixed_sdram()
106 	out_be32(&ddr->timing_cfg_0,	0x00220802);  in fixed_sdram()
107 	out_be32(&ddr->timing_cfg_1,	0x38377322);  in fixed_sdram()
108 	out_be32(&ddr->timing_cfg_2,	0x0fa044C7);  in fixed_sdram()
110 	out_be32(&ddr->sdram_cfg,	0x4300C000);  in fixed_sdram()
111 	out_be32(&ddr->sdram_cfg_2,	0x24401000);  in fixed_sdram()
113 	out_be32(&ddr->sdram_mode,	0x23C00542);  in fixed_sdram()
114 	out_be32(&ddr->sdram_mode_2,	0x00000000);  in fixed_sdram()
116 	out_be32(&ddr->sdram_interval,	0x05080100);  in fixed_sdram()
117 	out_be32(&ddr->sdram_md_cntl,	0x00000000);  in fixed_sdram()
118 	out_be32(&ddr->sdram_data_init,	0x00000000);  in fixed_sdram()
119 	out_be32(&ddr->sdram_clk_cntl,	0x03800000);  in fixed_sdram()
125 	  out_be32(&ddr->sdram_cfg, CONFIG_SYS_DDR_CONTROL | 0x20000000);  in fixed_sdram()