Lines Matching refs:CLK_EN
287 #define CLK_EN 0x1 macro
308 #define CLK_GATE_IP_CAM_ALL_EN ((CLK_EN << BIT_CAM_CLK_PIXELASYNCM1)\
309 | (CLK_EN << BIT_CAM_CLK_PIXELASYNCM0)\
310 | (CLK_EN << BIT_CAM_CLK_PPMUCAMIF)\
311 | (CLK_EN << BIT_CAM_CLK_QEFIMC3)\
312 | (CLK_EN << BIT_CAM_CLK_QEFIMC2)\
313 | (CLK_EN << BIT_CAM_CLK_QEFIMC1)\
314 | (CLK_EN << BIT_CAM_CLK_QEFIMC0)\
315 | (CLK_EN << BIT_CAM_CLK_SMMUJPEG)\
316 | (CLK_EN << BIT_CAM_CLK_SMMUFIMC3)\
317 | (CLK_EN << BIT_CAM_CLK_SMMUFIMC2)\
318 | (CLK_EN << BIT_CAM_CLK_SMMUFIMC1)\
319 | (CLK_EN << BIT_CAM_CLK_SMMUFIMC0)\
320 | (CLK_EN << BIT_CAM_CLK_JPEG)\
321 | (CLK_EN << BIT_CAM_CLK_CSIS1)\
322 | (CLK_EN << BIT_CAM_CLK_CSIS0)\
323 | (CLK_EN << BIT_CAM_CLK_FIMC3)\
324 | (CLK_EN << BIT_CAM_CLK_FIMC2)\
325 | (CLK_EN << BIT_CAM_CLK_FIMC1)\
326 | (CLK_EN << BIT_CAM_CLK_FIMC0))
335 #define CLK_GATE_IP_VP_ALL_EN ((CLK_EN << BIT_VP_CLK_PPMUTV)\
336 | (CLK_EN << BIT_VP_CLK_SMMUTV)\
337 | (CLK_EN << BIT_VP_CLK_HDMI)\
338 | (CLK_EN << BIT_VP_CLK_TVENC)\
339 | (CLK_EN << BIT_VP_CLK_MIXER)\
340 | (CLK_EN << BIT_VP_CLK_VP))
348 #define CLK_GATE_IP_MFC_ALL_EN ((CLK_EN << BIT_MFC_CLK_PPMUMFC_R)\
349 | (CLK_EN << BIT_MFC_CLK_PPMUMFC_L)\
350 | (CLK_EN << BIT_MFC_CLK_SMMUMFC_R)\
351 | (CLK_EN << BIT_MFC_CLK_SMMUMFC_L)\
352 | (CLK_EN << BIT_MFC_CLK_MFC))
358 #define CLK_GATE_IP_G3D_ALL_EN ((CLK_EN << BIT_G3D_CLK_QEG3D)\
359 | (CLK_EN << BIT_G3D_CLK_PPMUG3D)\
360 | (CLK_EN << BIT_G3D_CLK_G3D))
373 #define CLK_GATE_IP_IMAGE_ALL_EN ((CLK_EN << BIT_IMAGE_CLK_PPMUIMAGE)\
374 | (CLK_EN << BIT_IMAGE_CLK_QEMDMA)\
375 | (CLK_EN << BIT_IMAGE_CLK_QEROTATOR)\
376 | (CLK_EN << BIT_IMAGE_CLK_QEG2D)\
377 | (CLK_EN << BIT_IMAGE_CLK_SMMUMDMA)\
378 | (CLK_EN << BIT_IMAGE_CLK_SMMUROTATOR)\
379 | (CLK_EN << BIT_IMAGE_CLK_SMMUG2D)\
380 | (CLK_EN << BIT_IMAGE_CLK_MDMA)\
381 | (CLK_EN << BIT_IMAGE_CLK_ROTATOR)\
382 | (CLK_EN << BIT_IMAGE_CLK_G2D))
391 #define CLK_GATE_IP_LCD0_ALL_EN ((CLK_EN << BIT_LCD0_CLK_PPMULCD0)\
392 | (CLK_EN << BIT_LCD0_CLK_SMMUFIMD0)\
393 | (CLK_EN << BIT_LCD0_CLK_DSIM0)\
394 | (CLK_EN << BIT_LCD0_CLK_MDNIE0)\
395 | (CLK_EN << BIT_LCD0_CLK_MIE0)\
396 | (CLK_EN << BIT_LCD0_CLK_FIMD0))
405 #define CLK_GATE_IP_LCD1_ALL_EN ((CLK_EN << BIT_LCD1_CLK_PPMULCD1)\
406 | (CLK_EN << BIT_LCD1_CLK_SMMUFIMD1)\
407 | (CLK_EN << BIT_LCD1_CLK_DSIM1)\
408 | (CLK_EN << BIT_LCD1_CLK_MDNIE1)\
409 | (CLK_EN << BIT_LCD1_CLK_MIE1)\
410 | (CLK_EN << BIT_LCD1_CLK_FIMD1))
432 #define CLK_GATE_IP_FSYS_ALL_EN ((CLK_EN << BIT_FSYS_CLK_SMMUPCIE)\
433 | (CLK_EN << BIT_FSYS_CLK_PPMUFILE)\
434 | (CLK_EN << BIT_FSYS_CLK_NFCON)\
435 | (CLK_EN << BIT_FSYS_CLK_ONENAND)\
436 | (CLK_EN << BIT_FSYS_CLK_PCIE)\
437 | (CLK_EN << BIT_FSYS_CLK_USBDEVICE)\
438 | (CLK_EN << BIT_FSYS_CLK_USBHOST)\
439 | (CLK_EN << BIT_FSYS_CLK_SROMC)\
440 | (CLK_EN << BIT_FSYS_CLK_SATA)\
441 | (CLK_EN << BIT_FSYS_CLK_SDMMC4)\
442 | (CLK_EN << BIT_FSYS_CLK_SDMMC3)\
443 | (CLK_EN << BIT_FSYS_CLK_SDMMC2)\
444 | (CLK_EN << BIT_FSYS_CLK_SDMMC1)\
445 | (CLK_EN << BIT_FSYS_CLK_SDMMC0)\
446 | (CLK_EN << BIT_FSYS_CLK_TSI)\
447 | (CLK_EN << BIT_FSYS_CLK_SATAPHY)\
448 | (CLK_EN << BIT_FSYS_CLK_PCIEPHY)\
449 | (CLK_EN << BIT_FSYS_CLK_PDMA1)\
450 | (CLK_EN << BIT_FSYS_CLK_PDMA0))
455 #define CLK_GATE_IP_GPS_ALL_EN ((CLK_EN << BIT_GPS_CLK_SMMUGPS)\
456 | (CLK_EN << BIT_GPS_CLK_GPS))
488 #define CLK_GATE_IP_PERIL_ALL_EN ((CLK_EN << BIT_PERIL_CLK_MODEMIF)\
489 | (CLK_EN << BIT_PERIL_CLK_AC97)\
490 | (CLK_EN << BIT_PERIL_CLK_SPDIF)\
491 | (CLK_EN << BIT_PERIL_CLK_SLIMBUS)\
492 | (CLK_EN << BIT_PERIL_CLK_PWM)\
493 | (CLK_EN << BIT_PERIL_CLK_PCM2)\
494 | (CLK_EN << BIT_PERIL_CLK_PCM1)\
495 | (CLK_EN << BIT_PERIL_CLK_I2S2)\
496 | (CLK_EN << BIT_PERIL_CLK_I2S1)\
497 | (CLK_EN << BIT_PERIL_CLK_RESERVED0)\
498 | (CLK_EN << BIT_PERIL_CLK_SPI2)\
499 | (CLK_EN << BIT_PERIL_CLK_SPI1)\
500 | (CLK_EN << BIT_PERIL_CLK_SPI0)\
501 | (CLK_EN << BIT_PERIL_CLK_TSADC)\
502 | (CLK_EN << BIT_PERIL_CLK_I2CHDMI)\
503 | (CLK_EN << BIT_PERIL_CLK_I2C7)\
504 | (CLK_EN << BIT_PERIL_CLK_I2C6)\
505 | (CLK_EN << BIT_PERIL_CLK_I2C5)\
506 | (CLK_EN << BIT_PERIL_CLK_I2C4)\
507 | (CLK_EN << BIT_PERIL_CLK_I2C3)\
508 | (CLK_EN << BIT_PERIL_CLK_I2C2)\
509 | (CLK_EN << BIT_PERIL_CLK_I2C1)\
510 | (CLK_EN << BIT_PERIL_CLK_I2C0)\
511 | (CLK_EN << BIT_PERIL_CLK_RESERVED1)\
512 | (CLK_EN << BIT_PERIL_CLK_UART4)\
513 | (CLK_EN << BIT_PERIL_CLK_UART3)\
514 | (CLK_EN << BIT_PERIL_CLK_UART2)\
515 | (CLK_EN << BIT_PERIL_CLK_UART1)\
516 | (CLK_EN << BIT_PERIL_CLK_UART0))
537 #define CLK_GATE_IP_PERIR_ALL_EN ((CLK_EN << BIT_PERIR_CLK_TMU_APBIF)\
538 | (CLK_EN << BIT_PERIR_CLK_KEYIF)\
539 | (CLK_EN << BIT_PERIR_CLK_RTC)\
540 | (CLK_EN << BIT_PERIR_CLK_WDT)\
541 | (CLK_EN << BIT_PERIR_CLK_MCT)\
542 | (CLK_EN << BIT_PERIR_CLK_SECKEY)\
543 | (CLK_EN << BIT_PERIR_CLK_HDMI_CEC)\
544 | (CLK_EN << BIT_PERIR_CLK_TZPC5)\
545 | (CLK_EN << BIT_PERIR_CLK_TZPC4)\
546 | (CLK_EN << BIT_PERIR_CLK_TZPC3)\
547 | (CLK_EN << BIT_PERIR_CLK_TZPC2)\
548 | (CLK_EN << BIT_PERIR_CLK_TZPC1)\
549 | (CLK_EN << BIT_PERIR_CLK_TZPC0)\
550 | (CLK_EN << BIT_PERIR_CLK_CMU_DMCPART)\
551 | (CLK_EN << BIT_PERIR_CLK_RESERVED)\
552 | (CLK_EN << BIT_PERIR_CLK_CMU_APBIF)\
553 | (CLK_EN << BIT_PERIR_CLK_SYSREG)\
554 | (CLK_EN << BIT_PERIR_CLK_CHIP_ID))
565 #define CLK_GATE_BLOCK_ALL_EN ((CLK_EN << BIT_BLOCK_CLK_GPS)\
566 | (CLK_EN << BIT_BLOCK_CLK_RESERVED)\
567 | (CLK_EN << BIT_BLOCK_CLK_LCD1)\
568 | (CLK_EN << BIT_BLOCK_CLK_LCD0)\
569 | (CLK_EN << BIT_BLOCK_CLK_G3D)\
570 | (CLK_EN << BIT_BLOCK_CLK_MFC)\
571 | (CLK_EN << BIT_BLOCK_CLK_TV)\
572 | (CLK_EN << BIT_BLOCK_CLK_CAM))
597 | (CLK_EN << BIT_FSYS_CLK_PPMUFILE)\
598 | (CLK_EN << BIT_FSYS_CLK_USBDEVICE)\
599 | (CLK_EN << BIT_FSYS_CLK_USBHOST)\
600 | (CLK_EN << BIT_FSYS_CLK_SROMC)\
601 | (CLK_EN << BIT_FSYS_CLK_SDMMC2)\
602 | (CLK_EN << BIT_FSYS_CLK_SDMMC0)\
603 | (CLK_EN << BIT_FSYS_CLK_PDMA1)\
604 | (CLK_EN << BIT_FSYS_CLK_PDMA0))
607 | ~((CLK_EN << BIT_PERIL_CLK_AC97)\
608 | (CLK_EN << BIT_PERIL_CLK_SPDIF)\
609 | (CLK_EN << BIT_PERIL_CLK_I2C2)\
610 | (CLK_EN << BIT_PERIL_CLK_SLIMBUS)))
612 | ~((CLK_EN << BIT_PERIR_CLK_KEYIF)))