Lines Matching refs:r1
35 ldr r1, =0x9
36 str r1, [r0]
40 ldr r1, =S5PC100_VIC1_BASE @0xE4000000
46 str r3, [r1, #0x14] @INTENCLEAR
51 str r5, [r1, #0xc] @INTSELECT
56 str r5, [r1, #0xf00] @INTADDRESS
77 ldr r1, =0x00011110
78 str r1, [r8, #0x304]
79 ldr r1, =0x1
80 str r1, [r8, #0x308]
81 ldr r1, =0x00011301
82 str r1, [r8, #0x300]
85 ldr r1, =0xe10 @ Locktime : 0xe10 = 3600
86 str r1, [r8, #0x000] @ APLL_LOCK
87 str r1, [r8, #0x004] @ MPLL_LOCK
88 str r1, [r8, #0x008] @ EPLL_LOCK
89 str r1, [r8, #0x00C] @ HPLL_LOCK
92 ldr r1, =0x81bc0400 @ SDIV 0, PDIV 4, MDIV 444 (1332MHz)
93 str r1, [r8, #0x100]
95 ldr r1, =0x80590201 @ SDIV 1, PDIV 2, MDIV 89 (267MHz)
96 str r1, [r8, #0x104]
98 ldr r1, =0x80870303 @ SDIV 3, PDIV 3, MDIV 135 (67.5MHz)
99 str r1, [r8, #0x108]
101 ldr r1, =0x80600603
102 str r1, [r8, #0x10C]
105 ldr r1, =0x1111 @ A, M, E, HPLL Muxing
106 str r1, [r8, #0x200] @ CLK_SRC0
108 ldr r1, =0x1000001 @ Uart Clock & CLK48M Muxing
109 str r1, [r8, #0x204] @ CLK_SRC1
111 ldr r1, =0x9000 @ ARMCLK/4
112 str r1, [r8, #0x400] @ CLK_OUT
126 ldr r1, =0x22222222
127 str r1, [r0, #0x0] @ GPA0_CON
128 ldr r1, =0x00022222
129 str r1, [r0, #0x20] @ GPA1_CON
138 mov r1, #0x0
139 str r1, [r0]
140 mov r1, #0xff
141 str r1, [r0, #0x804]
142 str r1, [r0, #0x810]
145 str r1, [r0, #0x804]
146 str r1, [r0, #0x810]
147 str r1, [r0, #0x81C]
150 str r1, [r0, #0x804]
151 str r1, [r0, #0x810]