5  * SPDX-License-Identifier:	GPL-2.0+
23 #include <samsung/misc.h>
38 	/* Set GPA1 pin 1 to HI - enable XCL205 output */  in set_board_type()
44 	/* Set GPC1 pin 2 to IN - check XCL205 output state */  in set_board_type()
48 	/* XCL205 - needs some latch time */  in set_board_type()
51 	/* Check GPC1 pin2 - LED supplied by XCL205 - X2 only */  in set_board_type()
53 		gd->board_type = ODROID_TYPE_X2;  in set_board_type()
55 		gd->board_type = ODROID_TYPE_U3;  in set_board_type()
62 	return board_type[gd->board_type];  in get_board_type()
113 	clrsetbits_le32(&clk->src_cpu, clr_src_cpu, set);  in board_clock_init()
116 	while (readl(&clk->mux_stat_cpu) & MUX_STAT_CPU_CHANGING)  in board_clock_init()
123 	clrsetbits_le32(&clk->apll_con0, clr_pll_con0, set);  in board_clock_init()
126 	while (!(readl(&clk->apll_con0) & PLL_LOCKED_BIT))  in board_clock_init()
132 	clrsetbits_le32(&clk->src_cpu, clr_src_cpu, set);  in board_clock_init()
135 	while (readl(&clk->mux_stat_cpu) & MUX_STAT_CPU_CHANGING)  in board_clock_init()
156 	clrsetbits_le32(&clk->div_cpu0, clr, set);  in board_clock_init()
159 	while (readl(&clk->div_stat_cpu0) & DIV_STAT_CPU0_CHANGING)  in board_clock_init()
171 	clrsetbits_le32(&clk->div_cpu1, clr, set);  in board_clock_init()
174 	while (readl(&clk->div_stat_cpu1) & DIV_STAT_CPU1_CHANGING)  in board_clock_init()
197 	clrsetbits_le32(&clk->src_dmc, clr_src_dmc, set);  in board_clock_init()
200 	while (readl(&clk->mux_stat_dmc) & MUX_STAT_DMC_CHANGING)  in board_clock_init()
206 	clrsetbits_le32(&clk->mpll_con0, clr_pll_con0, set);  in board_clock_init()
209 	while (!(readl(&clk->mpll_con0) & PLL_LOCKED_BIT))  in board_clock_init()
217 	clrsetbits_le32(&clk->src_dmc, clr_src_dmc, set);  in board_clock_init()
220 	while (readl(&clk->mux_stat_dmc) & MUX_STAT_DMC_CHANGING)  in board_clock_init()
241 	clrsetbits_le32(&clk->div_dmc0, clr, set);  in board_clock_init()
244 	while (readl(&clk->div_stat_dmc0) & DIV_STAT_DMC0_CHANGING)  in board_clock_init()
264 	clrsetbits_le32(&clk->div_dmc1, clr, set);  in board_clock_init()
267 	while (readl(&clk->div_stat_dmc1) & DIV_STAT_DMC1_CHANGING)  in board_clock_init()
284 	clrsetbits_le32(&clk->src_peril0, clr, set);  in board_clock_init()
290 	 * For MOUTuart0-4: 800MHz  in board_clock_init()
297 	clrsetbits_le32(&clk->div_peril0, clr, set);  in board_clock_init()
299 	while (readl(&clk->div_stat_peril0) & DIV_STAT_PERIL0_CHANGING)  in board_clock_init()
306 	 * For MOUTmmc0-3 = 800 MHz (MPLL)  in board_clock_init()
316 	clrsetbits_le32(&clk->div_fsys1, clr, set);  in board_clock_init()
319 	while (readl(&clk->div_stat_fsys1) & DIV_STAT_FSYS1_CHANGING)  in board_clock_init()
326 	 * For MOUTmmc0-3 = 800 MHz (MPLL)  in board_clock_init()
336 	clrsetbits_le32(&clk->div_fsys2, clr, set);  in board_clock_init()
339 	while (readl(&clk->div_stat_fsys2) & DIV_STAT_FSYS2_CHANGING)  in board_clock_init()
352 	clrsetbits_le32(&clk->div_fsys3, clr, set);  in board_clock_init()
355 	while (readl(&clk->div_stat_fsys3) & DIV_STAT_FSYS3_CHANGING)  in board_clock_init()
474 	if (gd->board_type == ODROID_TYPE_U3)  in board_usb_init()
486 	debug("LAN9730 - Turning power buck 8 OFF and ON.\n");  in board_usb_init()
496 		pr_err("Regulator %s enable setting error: %d", dev->name, ret);  in board_usb_init()
502 		pr_err("Regulator %s value setting error: %d", dev->name, ret);  in board_usb_init()
508 		pr_err("Regulator %s value setting error: %d", dev->name, ret);  in board_usb_init()