Lines Matching +full:0 +full:xe0200000
19 * r7 has S5PC100 GPIO base, 0xE0300000
20 * r8 has real GPIO base, 0xE0300000, 0xE0200000 at S5PC100, S5PC110 repectively
29 mov r5, #0
36 mov r1, #0x00010000
48 and r1, r1, #0x000D0000
49 cmp r1, #(0x1 << 19) @ DEEPIDLE_WAKEUP
54 addeq r0, r8, #0x280 @ S5PC100_GPIO_J4
55 addne r0, r8, #0x2C0 @ S5PC110_GPIO_J4
56 ldr r1, [r0, #0x0] @ GPIO_CON_OFFSET
57 bic r1, r1, #(0xf << 4) @ 1 * 4-bit
58 orr r1, r1, #(0x1 << 4)
59 str r1, [r0, #0x0] @ GPIO_CON_OFFSET
61 ldr r1, [r0, #0x4] @ GPIO_DAT_OFFSET
63 str r1, [r0, #0x4] @ GPIO_DAT_OFFSET
75 * 0xE0F0_0000
76 * 0xE1F0_0000
77 * 0xF180_0000
78 * 0xF190_0000
79 * 0xF1A0_0000
80 * 0xF1B0_0000
81 * 0xF1C0_0000
82 * 0xF1D0_0000
83 * 0xF1E0_0000
84 * 0xF1F0_0000
85 * 0xFAF0_0000
87 ldr r0, =0xe0f00000
89 bic r1, r1, #0x1
92 ldr r0, =0xe1f00000
94 bic r1, r1, #0x1
97 ldr r0, =0xf1800000
99 bic r1, r1, #0x1
102 ldr r0, =0xf1900000
104 bic r1, r1, #0x1
107 ldr r0, =0xf1a00000
109 bic r1, r1, #0x1
112 ldr r0, =0xf1b00000
114 bic r1, r1, #0x1
117 ldr r0, =0xf1c00000
119 bic r1, r1, #0x1
122 ldr r0, =0xf1d00000
124 bic r1, r1, #0x1
127 ldr r0, =0xf1e00000
129 bic r1, r1, #0x1
132 ldr r0, =0xf1f00000
134 bic r1, r1, #0x1
137 ldr r0, =0xfaf00000
139 bic r1, r1, #0x1
146 ldr r0, =0xE010C300
147 ldr r1, =0x00800000
152 ldreq r0, =S5PC100_OTHERS @ 0xE0108200
153 ldrne r0, =S5PC110_OTHERS @ 0xE010E000
162 ldreq r0, =S5PC100_WATCHDOG_BASE @ 0xEA200000
163 ldrne r0, =S5PC110_WATCHDOG_BASE @ 0xE2700000
169 ldr r1, =0x9
173 ldreq r0, =S5PC100_VIC0_BASE @ 0xE4000000
174 ldrne r0, =S5PC110_VIC0_BASE @ 0xF2000000
175 add r1, r0, #0x00100000
176 add r2, r0, #0x00200000
179 mvn r3, #0x0
180 str r3, [r0, #0x14] @ INTENCLEAR
181 str r3, [r1, #0x14] @ INTENCLEAR
182 str r3, [r2, #0x14] @ INTENCLEAR
185 str r5, [r0, #0xc] @ INTSELECT
186 str r5, [r1, #0xc] @ INTSELECT
187 str r5, [r2, #0xc] @ INTSELECT
190 str r5, [r0, #0xf00] @ INTADDRESS
191 str r5, [r1, #0xf00] @ INTADDRESS
192 str r5, [r2, #0xf00] @ INTADDRESS
207 ldreq r0, =S5PC100_OTHERS @ 0xE0108200
208 ldrne r0, =S5PC110_OTHERS @ 0xE010E000
219 ldr r0, =0xE0100100 @ S5PC110_APLL_CON
244 ldr r0, =S5PC110_CLOCK_BASE @ 0xE0100000
251 ldr r1, =0xe10 @ Locktime : 0xe10 = 3600
252 str r1, [r0, #0x000] @ S5PC100_APLL_LOCK
253 str r1, [r0, #0x004] @ S5PC100_MPLL_LOCK
254 str r1, [r0, #0x008] @ S5PC100_EPLL_LOCK
255 str r1, [r0, #0x00C] @ S5PC100_HPLL_LOCK
258 ldr r1, =0x81bc0400 @ SDIV 0, PDIV 4, MDIV 444 (1333MHz)
259 str r1, [r0, #0x100]
261 ldr r1, =0x80590201 @ SDIV 1, PDIV 2, MDIV 89 (267MHz)
262 str r1, [r0, #0x104]
264 ldr r1, =0x80870303 @ SDIV 3, PDIV 3, MDIV 135 (67.5MHz)
265 str r1, [r0, #0x108]
267 ldr r1, =0x80600603 @ SDIV 3, PDIV 6, MDIV 96
268 str r1, [r0, #0x10C]
270 ldr r1, [r0, #0x300]
271 ldr r2, =0x00003fff
273 ldr r2, =0x00011301
276 str r1, [r0, #0x300]
277 ldr r1, [r0, #0x304]
278 ldr r2, =0x00011110
280 str r1, [r0, #0x304]
281 ldr r1, =0x00000001
282 str r1, [r0, #0x308]
285 ldr r1, =0x00001111 @ A, M, E, HPLL Muxing
286 str r1, [r0, #0x200] @ S5PC1XX_CLK_SRC0
290 ldr r0, =0xE010C000 @ S5PC110_PWR_CFG
293 ldr r1, =0xf
294 str r1, [r0, #0x100] @ S5PC110_OSC_FREQ
297 ldr r1, =0xffffffff
298 str r1, [r0, #0x110] @ S5PC110_MTC_STABLE
301 ldr r1, =0x3ff03ff
302 str r1, [r0, #0x114] @ S5PC110_CLAMP_STABLE
304 ldr r0, =S5PC110_CLOCK_BASE @ 0xE0100000
307 ldr r1, =0x14131330 @ 1:1:4:4, 1:4:5
308 str r1, [r0, #0x300]
309 ldr r1, =0x11110111 @ UART[3210]: MMC[3210]
310 str r1, [r0, #0x310]
313 ldr r1, =0x2cf @ Locktime : 30us
314 str r1, [r0, #0x000] @ S5PC110_APLL_LOCK
315 ldr r1, =0xe10 @ Locktime : 0xe10 = 3600
316 str r1, [r0, #0x008] @ S5PC110_MPLL_LOCK
317 str r1, [r0, #0x010] @ S5PC110_EPLL_LOCK
318 str r1, [r0, #0x020] @ S5PC110_VPLL_LOCK
321 ldr r1, =0x80C80601 @ 800MHz
322 str r1, [r0, #0x100]
324 ldr r1, =0x829B0C01 @ 667MHz
325 str r1, [r0, #0x108]
327 ldr r1, =0x80600602 @ 96MHz VSEL 0 P 6 M 96 S 2
328 str r1, [r0, #0x110]
330 ldr r1, =0x806C0603 @ 54MHz
331 str r1, [r0, #0x120]
334 ldr r1, =0x10001111 @ A, M, E, VPLL Muxing
335 str r1, [r0, #0x200] @ S5PC1XX_CLK_SRC0
338 ldr r1, =0x01000000 @ ONEDRAM_SEL[25:24] 1 SCLKMPLL
339 str r1, [r0, #0x218] @ S5PC110_CLK_SRC6
340 ldr r1, =0x30000000 @ ONEDRAM_RATIO[31:28] 3 + 1
341 str r1, [r0, #0x318] @ S5PC110_CLK_DIV6
344 add r2, r0, #0xE000 @ S5PC110_OTHERS
346 orr r1, r1, #(0x3 << 8) @ CLKOUT[9:8] 3 XUSBXTI
350 ldr r1, =0x8fefeeb @ DMC[1:0] PDMA0[3] IMEM[5]
351 str r1, [r0, #0x460] @ S5PC110_CLK_IP0
354 ldr r1, =0xe9fdf0f9 @ FIMD[0] USBOTG[16]
356 str r1, [r0, #0x464] @ S5PC110_CLK_IP1
359 ldr r1, =0xf75f7fc @ CORESIGHT[8] MODEM[9]
362 str r1, [r0, #0x468] @ S5PC110_CLK_IP2
365 ldr r1, =0x8eff038c @ I2C[8:6]
370 str r1, [r0, #0x46c] @ S5PC110_CLK_IP3
373 ldr r1, =0xfffffff1 @ CHIP_ID[0] TZPC[8:5]
374 str r1, [r0, #0x470] @ S5PC110_CLK_IP3
378 mov r2, #0x10000
385 ldreq r0, =0xE3800000
386 ldrne r0, =0xF1500000
387 ldr r1, =0x0
398 ldr r1, =0x22222222
399 str r1, [r0, #0x0] @ S5PC100_GPIO_A0_OFFSET
400 ldr r1, =0x00002222
401 str r1, [r0, #0x20] @ S5PC100_GPIO_A1_OFFSET
408 add r0, r8, #0x2A0 @ S5PC100_GPIO_K0_OFFSET
409 ldr r1, [r0, #0x0] @ S5PC1XX_GPIO_CON_OFFSET
410 bic r1, r1, #(0xf << 20) @ 20 = 5 * 4-bit
411 orr r1, r1, #(0x1 << 20) @ Output
412 str r1, [r0, #0x0] @ S5PC1XX_GPIO_CON_OFFSET
414 ldr r1, [r0, #0x8] @ S5PC1XX_GPIO_PULL_OFFSET
415 bic r1, r1, #(0x3 << 10) @ 10 = 5 * 2-bit
416 orr r1, r1, #(0x2 << 10) @ Pull-up enabled
417 str r1, [r0, #0x8] @ S5PC1XX_GPIO_PULL_OFFSET
419 ldr r1, [r0, #0x4] @ S5PC1XX_GPIO_DAT_OFFSET
421 str r1, [r0, #0x4] @ S5PC1XX_GPIO_DAT_OFFSET
427 * 0xE020'0360 is reserved address at S5PC100
430 add r0, r8, #0x360 @ S5PC110_GPIO_MP0_5_OFFSET
431 ldr r1, [r0, #0x0] @ S5PC1XX_GPIO_CON_OFFSET
432 bic r1, r1, #(0xf << 28) @ 28 = 7 * 4-bit
433 orr r1, r1, #(0x1 << 28) @ Output
434 str r1, [r0, #0x0] @ S5PC1XX_GPIO_CON_OFFSET
436 ldr r1, [r0, #0x8] @ S5PC1XX_GPIO_PULL_OFFSET
437 bic r1, r1, #(0x3 << 14) @ 14 = 7 * 2-bit
438 orr r1, r1, #(0x2 << 14) @ Pull-up enabled
439 str r1, [r0, #0x8] @ S5PC1XX_GPIO_PULL_OFFSET
441 ldr r1, [r0, #0x4] @ S5PC1XX_GPIO_DAT_OFFSET
443 str r1, [r0, #0x4] @ S5PC1XX_GPIO_DAT_OFFSET