renesas/ulcb/ulcb.c

7  * SPDX-License-Identifier: GPL-2.0+
16 #include <asm/mach-types.h>
23 #include <asm/arch/rcar-mstp.h>
40 	writel(0xA5A5A500, &rwdt->rwtcsra);  in s_init()
41 	writel(0xA5A5A500, &swdt->swtcsra);  in s_init()
49 #define TMU1_MSTP124		BIT(24)	/* non-secure */
88 /* R/- 32 Power status register 2(3DG) */
90 /* -/W 32 Power resume control register 2 (3DG) */
96 	gd->bd->bi_boot_params = CONFIG_SYS_TEXT_BASE + 0x50000;  in board_init()
105 	/* USB1 pull-up */  in board_init()
109 	/* EtherAVB Enable */  in board_init()
171 #error Only R8A7795 and R87796 is supported  in board_init()
184 	gd->ram_size = PHYS_SDRAM_1_SIZE;  in dram_init()
186 	gd->ram_size += PHYS_SDRAM_2_SIZE;  in dram_init()
189 	gd->ram_size += PHYS_SDRAM_3_SIZE;  in dram_init()
192 	gd->ram_size += PHYS_SDRAM_4_SIZE;  in dram_init()
200 	gd->bd->bi_dram[0].start = PHYS_SDRAM_1;  in dram_init_banksize()
201 	gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;  in dram_init_banksize()
203 	gd->bd->bi_dram[1].start = PHYS_SDRAM_2;  in dram_init_banksize()
204 	gd->bd->bi_dram[1].size = PHYS_SDRAM_2_SIZE;  in dram_init_banksize()
207 	gd->bd->bi_dram[2].start = PHYS_SDRAM_3;  in dram_init_banksize()
208 	gd->bd->bi_dram[2].size = PHYS_SDRAM_3_SIZE;  in dram_init_banksize()
211 	gd->bd->bi_dram[3].start = PHYS_SDRAM_4;  in dram_init_banksize()
212 	gd->bd->bi_dram[3].size = PHYS_SDRAM_4_SIZE;  in dram_init_banksize()