Lines Matching +full:0 +full:xe6160000

31 #define CPGWPCR	0xE6150904
32 #define CPGWPR  0xE615090C
41 	writel(0xA5A5A500, &rwdt->rwtcsra);  in s_init()
42 	writel(0xA5A5A500, &swdt->swtcsra);  in s_init()
44 	writel(0xA5A50000, CPGWPCR);  in s_init()
45 	writel(0xFFFFFFFF, CPGWPR);  in s_init()
59 #define SD0CKCR			0xE6150074
60 #define SD1CKCR			0xE6150078
61 #define SD2CKCR			0xE6150268
62 #define SD3CKCR			0xE615026C
86 	return 0;  in board_early_init_f()
91 #define	SYSC_PWRSR2	0xE6180100
93 #define	SYSC_PWRONCR2	0xE618010C
98 	gd->bd->bi_boot_params = CONFIG_SYS_TEXT_BASE + 0x50000;  in board_init()
109 	writel(0x0000001F, SYSC_PWRONCR2);  in board_init()
110 	while (readl(SYSC_PWRSR2) != 0x000003E0)  in board_init()
155 	gpio_direction_output(GPIO_GP_2_10, 0);  in board_init()
175 	gpio_direction_output(GPIO_GP_5_1, 1);	/* 1: 3.3V, 0: 1.8V */  in board_init()
196 	gpio_direction_output(GPIO_GP_5_3, 0);	/* 1: 3.3V, 0: 1.8V */  in board_init()
197 	gpio_direction_output(GPIO_GP_5_9, 0);	/* 1: 3.3V, 0: 1.8V */  in board_init()
224 	gpio_direction_output(GPIO_GP_3_14, 1);	/* 1: 3.3V, 0: 1.8V */  in board_init()
227 	return 0;  in board_init()
243 	return 0;  in dram_init()
248 	gd->bd->bi_dram[0].start = PHYS_SDRAM_1;  in dram_init_banksize()
249 	gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;  in dram_init_banksize()
262 	return 0;  in dram_init_banksize()
269 #define RST_BASE	0xE6160000
270 #define RST_CA57RESCNT	(RST_BASE + 0x40)
271 #define RST_CA53RESCNT	(RST_BASE + 0x44)
272 #define RST_RSTOUTCR	(RST_BASE + 0x58)
273 #define RST_CODE	0xA5A5000F
278 	i2c_reg_write(CONFIG_SYS_I2C_POWERIC_ADDR, 0x20, 0x80);  in reset_cpu()