Lines Matching +full:0 +full:x00020002
38 #define PMMR 0xE6060000
39 #define GPSR0 0xE6060004
40 #define GPSR1 0xE6060008
41 #define GPSR4 0xE6060014
42 #define GPSR5 0xE6060018
43 #define GPSR6 0xE606001C
44 #define GPSR7 0xE6060020
45 #define GPSR8 0xE6060024
46 #define GPSR9 0xE6060028
47 #define GPSR10 0xE606002C
48 #define GPSR11 0xE6060030
49 #define IPSR6 0xE6060058
50 #define PUPR2 0xE6060108
51 #define PUPR3 0xE606010C
52 #define PUPR4 0xE6060110
53 #define PUPR5 0xE6060114
54 #define PUPR7 0xE606011C
55 #define PUPR9 0xE6060124
56 #define PUPR10 0xE6060128
57 #define PUPR11 0xE606012C
59 #define CPG_PLL1CR 0xE6150028
60 #define CPG_PLL3CR 0xE61500DC
74 { GPSR0, 0xFFFFFFFF, 0x0BFFFFFF },
75 { GPSR1, 0xFFFFFFFF, 0x002FFFFF },
76 { GPSR4, 0xFFFFFFFF, 0x00000FFF },
77 { GPSR5, 0xFFFFFFFF, 0x00010FFF },
78 { GPSR6, 0xFFFFFFFF, 0x00010FFF },
79 { GPSR7, 0xFFFFFFFF, 0x00010FFF },
80 { GPSR8, 0xFFFFFFFF, 0x00010FFF },
81 { GPSR9, 0xFFFFFFFF, 0x00010FFF },
82 { GPSR10, 0xFFFFFFFF, 0x04006000 },
83 { GPSR11, 0xFFFFFFFF, 0x303FEFE0 },
84 { IPSR6, 0xFFFFFFFF, 0x0002000E },
88 { PUPR2, 0xFFFFFFFF, 0x00000000 },
89 { PUPR3, 0xFFFFFFFF, 0x0803FF40 },
90 { PUPR4, 0xFFFFFFFF, 0x0000FFFF },
91 { PUPR5, 0xFFFFFFFF, 0x00010FFF },
92 { PUPR7, 0xFFFFFFFF, 0x0001AFFF },
93 { PUPR9, 0xFFFFFFFF, 0x0001CFFF },
94 { PUPR10, 0xFFFFFFFF, 0xC0438001 },
95 { PUPR11, 0xFFFFFFFF, 0x0FC00007 },
112 volatile u32 i = 0x10000 * cnt; \
113 while (i > 0) \
124 if (cpu_type == 0x4A) { in s_init()
125 writel(0x4D000000, CPG_PLL1CR); in s_init()
126 writel(0x4F000000, CPG_PLL3CR); in s_init()
130 writel(0xA5A5A500, &rwdt->rwtcsra); in s_init()
131 writel(0xA5A5A500, &swdt->swtcsra); in s_init()
144 writel(0x00000020, &lbsc->cs0ctrl); in s_init()
145 writel(0x00000020, &lbsc->cs1ctrl); in s_init()
146 writel(0x00002020, &lbsc->ecs0ctrl); in s_init()
147 writel(0x00002020, &lbsc->ecs1ctrl); in s_init()
149 writel(0x2A103320, &lbsc->cswcr0); in s_init()
150 writel(0x2A103320, &lbsc->cswcr1); in s_init()
151 writel(0x19102110, &lbsc->ecswcr0); in s_init()
152 writel(0x19102110, &lbsc->ecswcr1); in s_init()
157 writel(0x0000A55A, &dbsc3_0->dbpdlck); in s_init()
159 writel(0x21000000, &dbsc3_0->dbcmd); /* opc=RstH (RESET => H) */ in s_init()
160 writel(0x11000000, &dbsc3_0->dbcmd); /* opc=PDXt(CKE=H) */ in s_init()
161 writel(0x10000000, &dbsc3_0->dbcmd); /* opc=PDEn(CKE=L) */ in s_init()
164 writel(0x00000001, &dbsc3_0->dbpdrga); in s_init()
165 writel(0x80000000, &dbsc3_0->dbpdrgd); in s_init()
167 writel(0x00000004, &dbsc3_0->dbpdrga); in s_init()
168 while ((readl(&dbsc3_0->dbpdrgd) & 0x00000001) != 0x00000001); in s_init()
171 writel(0x00000006, &dbsc3_0->dbpdrga); in s_init()
172 writel(0x0001C000, &dbsc3_0->dbpdrgd); // > DDR1440 in s_init()
175 writel(0x0000000F, &dbsc3_0->dbpdrga); in s_init()
176 writel(0x00181EE4, &dbsc3_0->dbpdrgd); in s_init()
179 writel(0x00000010, &dbsc3_0->dbpdrga); in s_init()
180 writel(0xF00464DB, &dbsc3_0->dbpdrgd); in s_init()
182 writel(0x00000061, &dbsc3_0->dbpdrga); in s_init()
183 writel(0x0000008D, &dbsc3_0->dbpdrgd); in s_init()
186 writel(0x00000001, &dbsc3_0->dbpdrga); in s_init()
187 writel(0x00000073, &dbsc3_0->dbpdrgd); in s_init()
189 writel(0x00000007, &dbsc3_0->dbkind); in s_init()
190 writel(0x0F030A02, &dbsc3_0->dbconf0); in s_init()
191 writel(0x00000001, &dbsc3_0->dbphytype); in s_init()
192 writel(0x00000000, &dbsc3_0->dbbl); in s_init()
194 writel(0x0000000B, &dbsc3_0->dbtr0); // tCL=11 in s_init()
195 writel(0x00000008, &dbsc3_0->dbtr1); // tCWL=8 in s_init()
196 writel(0x00000000, &dbsc3_0->dbtr2); // tAL=0 in s_init()
197 writel(0x0000000B, &dbsc3_0->dbtr3); // tRCD=11 in s_init()
198 writel(0x000C000B, &dbsc3_0->dbtr4); // tRPA=12,tRP=11 in s_init()
199 writel(0x00000027, &dbsc3_0->dbtr5); // tRC = 39 in s_init()
200 writel(0x0000001C, &dbsc3_0->dbtr6); // tRAS = 28 in s_init()
201 writel(0x00000006, &dbsc3_0->dbtr7); // tRRD = 6 in s_init()
202 writel(0x00000020, &dbsc3_0->dbtr8); // tRFAW = 32 in s_init()
203 writel(0x00000008, &dbsc3_0->dbtr9); // tRDPR = 8 in s_init()
204 writel(0x0000000C, &dbsc3_0->dbtr10); // tWR = 12 in s_init()
205 writel(0x00000009, &dbsc3_0->dbtr11); // tRDWR = 9 in s_init()
206 writel(0x00000012, &dbsc3_0->dbtr12); // tWRRD = 18 in s_init()
207 writel(0x000000D0, &dbsc3_0->dbtr13); // tRFC = 208 in s_init()
208 writel(0x00140005, &dbsc3_0->dbtr14); in s_init()
209 writel(0x00050004, &dbsc3_0->dbtr15); in s_init()
210 writel(0x70233005, &dbsc3_0->dbtr16); /* DQL = 35, WDQL = 5 */ in s_init()
211 writel(0x000C0000, &dbsc3_0->dbtr17); in s_init()
212 writel(0x00000300, &dbsc3_0->dbtr18); in s_init()
213 writel(0x00000040, &dbsc3_0->dbtr19); in s_init()
214 writel(0x00000001, &dbsc3_0->dbrnk0); in s_init()
215 writel(0x00020001, &dbsc3_0->dbadj0); in s_init()
216 writel(0x20082004, &dbsc3_0->dbadj2); /* blanche QoS rev0.1 */ in s_init()
217 writel(0x00020002, &dbsc3_0->dbwt0cnf0); /* 1600 */ in s_init()
218 writel(0x0000001F, &dbsc3_0->dbwt0cnf4); in s_init()
220 while ((readl(&dbsc3_0->dbdfistat) & 0x00000001) != 0x00000001); in s_init()
221 writel(0x00000011, &dbsc3_0->dbdficnt); in s_init()
224 writel(0x00000003, &dbsc3_0->dbpdrga); in s_init()
225 writel(0x0300C4E1, &dbsc3_0->dbpdrgd); /* DDR3 */ in s_init()
228 writel(0x00000023, &dbsc3_0->dbpdrga); in s_init()
229 writel(0x00FCDB60, &dbsc3_0->dbpdrgd); in s_init()
231 writel(0x00000011, &dbsc3_0->dbpdrga); in s_init()
232 writel(0x1000040B, &dbsc3_0->dbpdrgd); in s_init()
234 /* DTPR0 :DRAM Timing Parameters Register 0 */ in s_init()
235 writel(0x00000012, &dbsc3_0->dbpdrga); in s_init()
236 writel(0x9D9CBB66, &dbsc3_0->dbpdrgd); in s_init()
239 writel(0x00000013, &dbsc3_0->dbpdrga); in s_init()
240 writel(0x1A868400, &dbsc3_0->dbpdrgd); in s_init()
243 writel(0x00000014, &dbsc3_0->dbpdrga); in s_init()
244 writel(0x300214D8, &dbsc3_0->dbpdrgd); in s_init()
246 /* MR0 :Mode Register 0 */ in s_init()
247 writel(0x00000015, &dbsc3_0->dbpdrga); in s_init()
248 writel(0x00000D70, &dbsc3_0->dbpdrgd); in s_init()
251 writel(0x00000016, &dbsc3_0->dbpdrga); in s_init()
252 writel(0x00000004, &dbsc3_0->dbpdrgd); /* DRAM Drv 40ohm */ in s_init()
255 writel(0x00000017, &dbsc3_0->dbpdrga); in s_init()
256 writel(0x00000018, &dbsc3_0->dbpdrgd); /* CWL=8 */ in s_init()
259 writel(0x0000001A, &dbsc3_0->dbpdrga); in s_init()
260 writel(0x910035C7, &dbsc3_0->dbpdrgd); in s_init()
262 /* PGSR0 :PHY General Status Registers 0 */ in s_init()
263 writel(0x00000004, &dbsc3_0->dbpdrga); in s_init()
264 while ((readl(&dbsc3_0->dbpdrgd) & 0x00000001) != 0x00000001); in s_init()
267 writel(0x00000001, &dbsc3_0->dbpdrga); in s_init()
268 writel(0x00000181, &dbsc3_0->dbpdrgd); in s_init()
271 writel(0x11000000, &dbsc3_0->dbcmd); /* opc=PDXt(CKE=H) */ in s_init()
273 /* PGSR0 :PHY General Status Registers 0 */ in s_init()
274 writel(0x00000004, &dbsc3_0->dbpdrga); in s_init()
275 while ((readl(&dbsc3_0->dbpdrgd) & 0x00000001) != 0x00000001); in s_init()
278 writel(0x00000001, &dbsc3_0->dbpdrga); in s_init()
279 writel(0x0000FE01, &dbsc3_0->dbpdrgd); in s_init()
281 /* Bus control 0 */ in s_init()
282 writel(0x00000000, &dbsc3_0->dbbs0cnt1); in s_init()
284 writel(0x01004C20, &dbsc3_0->dbcalcnf); in s_init()
286 writel(0x014000AA, &dbsc3_0->dbcaltr); in s_init()
288 writel(0x00000140, &dbsc3_0->dbrfcnf0); in s_init()
289 writel(0x00081860, &dbsc3_0->dbrfcnf1); in s_init()
290 writel(0x00010000, &dbsc3_0->dbrfcnf2); in s_init()
292 /* PGSR0 :PHY General Status Registers 0 */ in s_init()
293 writel(0x00000004, &dbsc3_0->dbpdrga); in s_init()
294 while ((readl(&dbsc3_0->dbpdrgd) & 0x00000001) != 0x00000001); in s_init()
297 writel(0x00000001, &dbsc3_0->dbrfen); in s_init()
299 writel(0x00000001, &dbsc3_0->dbacen); in s_init()
302 writel(0x00000000, &dbsc3_0->dbpdlck); in s_init()
323 return 0; in board_early_init_f()
330 gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; in board_init()
403 return 0; in board_init()
411 int rc = 0; in board_eth_init()
419 rc = smc911x_initialize(0, CONFIG_SMC911X_BASE); in board_eth_init()
422 dev = eth_get_dev_by_index(0); in board_eth_init()
453 ret = sh_sdhi_init(CONFIG_SYS_SH_SDHI0_BASE, 0, in board_mmc_init()
464 gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE; in dram_init()
467 return 0; in dram_init()