62 #define IMX6Q_DRIVE_STRENGTH	0x30
67 	return 0;  in dram_init()
194 	int ret = 0;  in board_mmc_getcd()
215 	for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) {  in board_mmc_init()
217 		case 0:  in board_mmc_init()
219 			usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);  in board_mmc_init()
238 	return 0;  in board_mmc_init()
251 	gpio_direction_output(ENET_PHY_RESET_GPIO, 0);  in setup_iomux_enet()
288 			MXC_CCM_CS2CDR_ENFC_CLK_PODF(0) |  in setup_gpmi_nand()
316 	for (i = 0, rev = 0; i < 4; i++)  in get_board_rev()
324 	if (bus != 2 || (cs != 0))  in board_spi_cs_gpio()
341 	return 0;  in board_early_init_f()
347 	gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;  in board_init()
350 	setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info);  in board_init()
362 	return 0;  in board_init()
371  *  BOOT_CFG1[5] = 0 - raw NAND
372  *  BOOT_CFG1[4] = 0 - default pad settings
374  *  BOOT_CFG1[1:0] = 00 - Row Address Cycles = 3
377  *  BOOT_CFG2[0] = 0 - Reset time 12ms
381 	{"nand", MAKE_CFGVAL(0x80, 0x02, 0x00, 0x00)},
382 	{"mmc0",  MAKE_CFGVAL(0x40, 0x20, 0x00, 0x00)},
383 	{NULL, 0},
397 	return 0;  in board_late_init()
415 	gpio_direction_output(MX6_PHYFLEX_ERR006282, 0);  in phyflex_err006282_workaround()
419 	gpio_set_value(MX6_PHYFLEX_ERR006282, 0);  in phyflex_err006282_workaround()
425 	.dram_sdclk_0 = 0x00000030,
426 	.dram_sdclk_1 = 0x00000030,
427 	.dram_cas = 0x00000030,
428 	.dram_ras = 0x00000030,
429 	.dram_reset = 0x00000030,
430 	.dram_sdcke0 = 0x00003000,
431 	.dram_sdcke1 = 0x00003000,
432 	.dram_sdba2 = 0x00000030,
433 	.dram_sdodt0 = 0x00000030,
434 	.dram_sdodt1 = 0x00000030,
436 	.dram_sdqs0 = 0x00000028,
437 	.dram_sdqs1 = 0x00000028,
438 	.dram_sdqs2 = 0x00000028,
439 	.dram_sdqs3 = 0x00000028,
440 	.dram_sdqs4 = 0x00000028,
441 	.dram_sdqs5 = 0x00000028,
442 	.dram_sdqs6 = 0x00000028,
443 	.dram_sdqs7 = 0x00000028,
444 	.dram_dqm0 = 0x00000028,
445 	.dram_dqm1 = 0x00000028,
446 	.dram_dqm2 = 0x00000028,
447 	.dram_dqm3 = 0x00000028,
448 	.dram_dqm4 = 0x00000028,
449 	.dram_dqm5 = 0x00000028,
450 	.dram_dqm6 = 0x00000028,
451 	.dram_dqm7 = 0x00000028,
455 	.grp_ddr_type =  0x000C0000,
456 	.grp_ddrmode_ctl =  0x00020000,
457 	.grp_ddrpke =  0x00000000,
460 	.grp_ddrmode =  0x00020000,
461 	.grp_b0ds = 0x00000028,
462 	.grp_b1ds = 0x00000028,
463 	.grp_b2ds = 0x00000028,
464 	.grp_b3ds = 0x00000028,
465 	.grp_b4ds = 0x00000028,
466 	.grp_b5ds = 0x00000028,
467 	.grp_b6ds = 0x00000028,
468 	.grp_b7ds = 0x00000028,
472 	.p0_mpwldectrl0 =  0x00110011,
473 	.p0_mpwldectrl1 =  0x00240024,
474 	.p1_mpwldectrl0 =  0x00260038,
475 	.p1_mpwldectrl1 =  0x002C0038,
476 	.p0_mpdgctrl0 =  0x03400350,
477 	.p0_mpdgctrl1 =  0x03440340,
478 	.p1_mpdgctrl0 =  0x034C0354,
479 	.p1_mpdgctrl1 =  0x035C033C,
480 	.p0_mprddlctl =  0x322A2A2A,
481 	.p1_mprddlctl =  0x302C2834,
482 	.p0_mpwrdlctl =  0x34303834,
483 	.p1_mpwrdlctl =  0x422A3E36,
544 	writel(0x00C03F3F, &ccm->CCGR0);  in ccgr_init()
545 	writel(0x0030FC03, &ccm->CCGR1);  in ccgr_init()
546 	writel(0x0FFFC000, &ccm->CCGR2);  in ccgr_init()
547 	writel(0x3FF00000, &ccm->CCGR3);  in ccgr_init()
548 	writel(0x00FFF300, &ccm->CCGR4);  in ccgr_init()
549 	writel(0x0F0000C3, &ccm->CCGR5);  in ccgr_init()
550 	writel(0x000003FF, &ccm->CCGR6);  in ccgr_init()
566 	usdhc_cfg[0].esdhc_base = USDHC3_BASE_ADDR;  in board_mmc_init()
567 	usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);  in board_mmc_init()
568 	usdhc_cfg[0].max_bus_width = 4;  in board_mmc_init()
569 	gd->arch.sdhc_clk = usdhc_cfg[0].sdhc_clk;  in board_mmc_init()
571 	return fsl_esdhc_initialize(bis, &usdhc_cfg[0]);  in board_mmc_init()
577 	spl_boot_list[0] = spl_boot_device();  in board_boot_order()
578 	printf("Boot device %x\n", spl_boot_list[0]);  in board_boot_order()
579 	switch (spl_boot_list[0]) {  in board_boot_order()
588 		printf("Boot device %x\n", spl_boot_list[0]);  in board_boot_order()
598 #define RAM_TEST_PATTERN	0xaa5555aa
607 	for (i = 0; i < 2; i++) {  in pfla02_detect_chiptype()
611 		*p1 = 0;  in pfla02_detect_chiptype()
631 		/* width of data bus:0=16,1=32,2=64 */  in board_init_f()
648 		.sde_to_rst = 0x10,	/* 14 cycles, 200us (JEDEC default) */  in board_init_f()
649 		.rst_to_cke = 0x23,	/* 33 cycles, 500us (JEDEC default) */  in board_init_f()
701 	memset(__bss_start, 0, __bss_end - __bss_start);  in board_init_f()
706 	board_init_r(NULL, 0);  in board_init_f()