4  * SPDX-License-Identifier:	GPL-2.0+
9 #include <asm/arch/imx-regs.h>
10 #include <asm/arch/iomux-vf610.h>
11 #include <asm/arch/ddrmc-vf610.h>
18 #include <i2c.h>
23  * Default DDR pad settings in arch/arm/include/asm/arch-vf610/iomux-vf610.h
118 	{ 0, -1 }
121 /* PHY settings -- most of them differ from default in imx-regs.h */
150 	{ 0, -1 }
329 	gd->ram_size = get_ram_size((void *)PHYS_SDRAM, PHYS_SDRAM_SIZE);  in dram_init()
366  * I2C2 is the only I2C used, on pads PTA22/PTA23.
468 	clrsetbits_le32(&ccm->ccgr0, CCM_REG_CTRL_MASK,  in clock_init()
470 	clrsetbits_le32(&ccm->ccgr1, CCM_REG_CTRL_MASK,  in clock_init()
472 	clrsetbits_le32(&ccm->ccgr2, CCM_REG_CTRL_MASK,  in clock_init()
477 	clrsetbits_le32(&ccm->ccgr3, CCM_REG_CTRL_MASK,  in clock_init()
479 	clrsetbits_le32(&ccm->ccgr4, CCM_REG_CTRL_MASK,  in clock_init()
482 	clrsetbits_le32(&ccm->ccgr6, CCM_REG_CTRL_MASK,  in clock_init()
484 	clrsetbits_le32(&ccm->ccgr7, CCM_REG_CTRL_MASK,  in clock_init()
486 	clrsetbits_le32(&ccm->ccgr9, CCM_REG_CTRL_MASK,  in clock_init()
488 	clrsetbits_le32(&ccm->ccgr10, CCM_REG_CTRL_MASK,  in clock_init()
491 	clrsetbits_le32(&anadig->pll2_ctrl, ANADIG_PLL2_CTRL_POWERDOWN,  in clock_init()
493 	clrsetbits_le32(&anadig->pll1_ctrl, ANADIG_PLL1_CTRL_POWERDOWN,  in clock_init()
496 	clrsetbits_le32(&ccm->ccr, CCM_CCR_OSCNT_MASK,  in clock_init()
498 	clrsetbits_le32(&ccm->ccsr, CCM_REG_CTRL_MASK,  in clock_init()
505 	clrsetbits_le32(&ccm->cacrr, CCM_REG_CTRL_MASK,  in clock_init()
508 	clrsetbits_le32(&ccm->cscmr1, CCM_REG_CTRL_MASK,  in clock_init()
512 	clrsetbits_le32(&ccm->cscdr1, CCM_REG_CTRL_MASK,  in clock_init()
514 	clrsetbits_le32(&ccm->cscdr2, CCM_REG_CTRL_MASK,  in clock_init()
517 	clrsetbits_le32(&ccm->cscdr3, CCM_REG_CTRL_MASK,  in clock_init()
522 	clrsetbits_le32(&ccm->cscmr2, CCM_REG_CTRL_MASK,  in clock_init()
532 		writew(MSCM_IRSPRC_CP0_EN, &mscmir->irsprc[i]);  in mscm_init()
537 	if (phydev->drv->config)  in board_phy_config()
538 		phydev->drv->config(phydev);  in board_phy_config()
561 	gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;  in board_init()
570 	setbits_le32(&scsc->sosc_ctr, SCSC_SOSC_CTR_SOSC_EN);  in board_init()
577 	puts("Board: PCM-052\n");  in checkboard()
588 	argc--; argv++;  in do_m4go()
591 	 * Parse provided address - default to load_addr in case not provided.  in do_m4go()
614 	"start the secondary Cortex-M4 from scatter file image",
616 	"    - start secondary Cortex-M4 core using a scatter file image\n"