Lines Matching +full:inter +full:- +full:processor

2  modified from SH-IPL+g
9  * SPDX-License-Identifier:	GPL-2.0+
14 #include <asm/processor.h>
18 #define BCR2_D_VALUE	0x2FFC		/* Area 1-6 width: 32/32/32/32/32/16 */
27 #define WCR3_D_VALUE	0x01777771	/* A6: 0-1 A5: 1-3 A4: 1-3 A3: 1-3
28 					   A2: 1-3 A1: 1-3 A0: 0-1 */
30 #define SDMR3_ADDRESS	0xFF940088	/* SDMR3 address on 32-bit bus */
31 #define MCR_D1_VALUE	0x100901B4	/* SDRAM 32-bit, CAS/RAS Refresh, .. */
34 #define BCR2_D_VALUE	0x2E3C		/* Area 1-6 width: 32/32/64/16/32/16 */
38 #define WCR3_D_VALUE	0x01717771	/* A6: 0-1 A5: 1-3 A4: 0-1 A3: 1-3
39 					   A2: 1-3 A1: 1-3 A0: 0-1 */
41 #define SDMR3_ADDRESS	0xFF940110	/* SDMR3 address on 64-bit bus */
42 #define MCR_D1_VALUE	0x8801001C	/* SDRAM 64-bit, CAS/RAS Refresh, .. */
121 WCR1_D:		.long	WCR1_D_VALUE	/* Inter-area or turnaround wait states */
123 WCR2_D:		.long	WCR2_D_VALUE	/* Per-area access and burst wait states */