Lines Matching +full:0 +full:x00000012

57 	mov	#0, r0
72 FRQCR_D:	.word	0x1103		/* I:B:P=8:4:2 */
73 WTCNT_D:	.word	0x5A00		/* start counting at zero */
74 WTCSR_D:	.word	0xA507		/* divide by 4096 */
80 CS0BCR_D:	.long	0x12490400
82 CS0WCR_D:	.long	0x00000340
88 /* CS3BCR = 0x10004400, minimum idle cycles, SDRAM, 16 bit */
89 CS3BCR_D:	.long	0x10004400
91 CS3WCR_D:	.long	0x00000091
93 SDCR_D1:	.long	0x00000012
94 SDCR_D2:	.long	0x00000812	/* refresh */
95 RTCSR_D:	.long	0xA55A0008	/* 1/4, once */
96 RTCNT_D:	.long	0xA55A005D	/* count 93 */
97 RTCOR_D:	.long	0xa55a005d	/* count 93 */
99 SDMR3_D:	.long	0x440
105 FRQCR_A:	.long	0xA415FF80
106 WTCNT_A:	.long	0xA415FF84
107 WTCSR_A:	.long	0xA415FF86
109 #define BSC_BASE	0xA4FD0000
110 CS0BCR_A:	.long	BSC_BASE + 0x04
111 CS3BCR_A:	.long	BSC_BASE + 0x0C
112 CS0WCR_A:	.long	BSC_BASE + 0x24
113 CS3WCR_A:	.long	BSC_BASE + 0x2C
114 SDCR_A:		.long	BSC_BASE + 0x44
115 RTCSR_A:	.long	BSC_BASE + 0x48
116 RTCNT_A:	.long	BSC_BASE + 0x4C
117 RTCOR_A:	.long	BSC_BASE + 0x50
118 SDMR3_A:	.long	BSC_BASE + 0x5000