441 	dma_state->dma_cmd = cmd;  in dma_state_process()
445 					  u32 dma_cmd)  in dma_state_process_dma_command()  argument
447 	dma_state->dma_cmd = dma_cmd;  in dma_state_process_dma_command()
448 	switch (dma_cmd) {  in dma_state_process_dma_command()
463 	union scc_cmd dma_cmd;  in scc_takeover_dma()  local
465 	dma_cmd.reg = 0;  in scc_takeover_dma()
468 	dma_cmd.bits.action = DMA_TAKEOVER;  in scc_takeover_dma()
469 	dma_cmd.bits.id = dma_id;  in scc_takeover_dma()
470 	dma_cmd.bits.rid = TO_DMA_CFG;	/* this is DMA_CFG register takeover */  in scc_takeover_dma()
472 		dma_cmd.bits.drs = DMA_WRITE;  in scc_takeover_dma()
474 	reg_write(SCC_CMD(scc_descriptor_table[id].base_address), dma_cmd.reg);  in scc_takeover_dma()
479 	union scc_cmd dma_cmd;  in scc_dma_cmd()  local
485 	dma_cmd.reg = 0;  in scc_dma_cmd()
488 	dma_cmd.bits.action = cmd;  in scc_dma_cmd()
489 	dma_cmd.bits.id = dma_id;  in scc_dma_cmd()
491 		dma_cmd.bits.drs = DMA_WRITE;  in scc_dma_cmd()
501 	reg_write(SCC_CMD(scc_descriptor_table[id].base_address), dma_cmd.reg);  in scc_dma_cmd()