Lines Matching refs:en1
18 union dcgu_clk_en1 en1; in dcgu_set_clk_switch() local
37 en1.reg = reg_read(DCGU_CLK_EN1(DCGU_BASE)); in dcgu_set_clk_switch()
41 en1.bits.en_clkmsmc = enable; in dcgu_set_clk_switch()
44 en1.bits.en_clkssi_s = enable; in dcgu_set_clk_switch()
47 en1.bits.en_clkssi_m = enable; in dcgu_set_clk_switch()
50 en1.bits.en_clksmc = enable; in dcgu_set_clk_switch()
53 en1.bits.en_clkebi = enable; in dcgu_set_clk_switch()
56 en1.bits.en_usbpll = enable; in dcgu_set_clk_switch()
59 en1.bits.en_clkusb60 = enable; in dcgu_set_clk_switch()
62 en1.bits.en_clkusb24 = enable; in dcgu_set_clk_switch()
65 en1.bits.en_clkuart2 = enable; in dcgu_set_clk_switch()
68 en1.bits.en_clkuart1 = enable; in dcgu_set_clk_switch()
71 en1.bits.en_clkperi20 = enable; in dcgu_set_clk_switch()
77 en1.bits.en_clk_i2s_dly = enable; in dcgu_set_clk_switch()
80 en1.bits.en_clk_scc_abp = enable; in dcgu_set_clk_switch()
83 en1.bits.en_clk_dtv_spdo = enable; in dcgu_set_clk_switch()
86 en1.bits.en_clkad = enable; in dcgu_set_clk_switch()
89 en1.bits.en_clkmvd = enable; in dcgu_set_clk_switch()
92 en1.bits.en_clktsd = enable; in dcgu_set_clk_switch()
95 en1.bits.en_clkga = enable; in dcgu_set_clk_switch()
98 en1.bits.en_clkdvp = enable; in dcgu_set_clk_switch()
101 en1.bits.en_clkmr2 = enable; in dcgu_set_clk_switch()
104 en1.bits.en_clkmr1 = enable; in dcgu_set_clk_switch()
123 reg_write(DCGU_CLK_EN1(DCGU_BASE), en1.reg); in dcgu_set_clk_switch()
124 en1.reg = reg_read(DCGU_CLK_EN1(DCGU_BASE)); in dcgu_set_clk_switch()