17 	u32 enable;  in dcgu_set_clk_switch()  local
23 		enable = 1;  in dcgu_set_clk_switch()
26 		enable = 0;  in dcgu_set_clk_switch()
41 		en1.bits.en_clkmsmc = enable;  in dcgu_set_clk_switch()
44 		en1.bits.en_clkssi_s = enable;  in dcgu_set_clk_switch()
47 		en1.bits.en_clkssi_m = enable;  in dcgu_set_clk_switch()
50 		en1.bits.en_clksmc = enable;  in dcgu_set_clk_switch()
53 		en1.bits.en_clkebi = enable;  in dcgu_set_clk_switch()
56 		en1.bits.en_usbpll = enable;  in dcgu_set_clk_switch()
59 		en1.bits.en_clkusb60 = enable;  in dcgu_set_clk_switch()
62 		en1.bits.en_clkusb24 = enable;  in dcgu_set_clk_switch()
65 		en1.bits.en_clkuart2 = enable;  in dcgu_set_clk_switch()
68 		en1.bits.en_clkuart1 = enable;  in dcgu_set_clk_switch()
71 		en1.bits.en_clkperi20 = enable;  in dcgu_set_clk_switch()
74 		en2.bits.en_clkcpu = enable;  in dcgu_set_clk_switch()
77 		en1.bits.en_clk_i2s_dly = enable;  in dcgu_set_clk_switch()
80 		en1.bits.en_clk_scc_abp = enable;  in dcgu_set_clk_switch()
83 		en1.bits.en_clk_dtv_spdo = enable;  in dcgu_set_clk_switch()
86 		en1.bits.en_clkad = enable;  in dcgu_set_clk_switch()
89 		en1.bits.en_clkmvd = enable;  in dcgu_set_clk_switch()
92 		en1.bits.en_clktsd = enable;  in dcgu_set_clk_switch()
95 		en1.bits.en_clkga = enable;  in dcgu_set_clk_switch()
98 		en1.bits.en_clkdvp = enable;  in dcgu_set_clk_switch()
101 		en1.bits.en_clkmr2 = enable;  in dcgu_set_clk_switch()
104 		en1.bits.en_clkmr1 = enable;  in dcgu_set_clk_switch()
133 	u32 enable;  in dcgu_set_reset_switch()  local
137 		enable = 1;  in dcgu_set_reset_switch()
140 		enable = 0;  in dcgu_set_reset_switch()
151 		val.bits.swreset_clkmsmc = enable;  in dcgu_set_reset_switch()
154 		val.bits.swreset_clkssi_s = enable;  in dcgu_set_reset_switch()
157 		val.bits.swreset_clkssi_m = enable;  in dcgu_set_reset_switch()
160 		val.bits.swreset_clksmc = enable;  in dcgu_set_reset_switch()
163 		val.bits.swreset_clkebi = enable;  in dcgu_set_reset_switch()
166 		val.bits.swreset_clkusb60 = enable;  in dcgu_set_reset_switch()
169 		val.bits.swreset_clkusb24 = enable;  in dcgu_set_reset_switch()
172 		val.bits.swreset_clkuart2 = enable;  in dcgu_set_reset_switch()
175 		val.bits.swreset_clkuart1 = enable;  in dcgu_set_reset_switch()
178 		val.bits.swreset_pwm = enable;  in dcgu_set_reset_switch()
181 		val.bits.swreset_gpt = enable;  in dcgu_set_reset_switch()
184 		val.bits.swreset_i2c2 = enable;  in dcgu_set_reset_switch()
187 		val.bits.swreset_i2c1 = enable;  in dcgu_set_reset_switch()
190 		val.bits.swreset_gpio2 = enable;  in dcgu_set_reset_switch()
193 		val.bits.swreset_gpio1 = enable;  in dcgu_set_reset_switch()
196 		val.bits.swreset_clkcpu = enable;  in dcgu_set_reset_switch()
199 		val.bits.swreset_clk_i2s_dly = enable;  in dcgu_set_reset_switch()
202 		val.bits.swreset_clk_scc_abp = enable;  in dcgu_set_reset_switch()
205 		val.bits.swreset_clk_dtv_spdo = enable;  in dcgu_set_reset_switch()
208 		val.bits.swreset_clkad = enable;  in dcgu_set_reset_switch()
211 		val.bits.swreset_clkmvd = enable;  in dcgu_set_reset_switch()
214 		val.bits.swreset_clktsd = enable;  in dcgu_set_reset_switch()
217 		val.bits.swreset_clktsio = enable;  in dcgu_set_reset_switch()
220 		val.bits.swreset_clkga = enable;  in dcgu_set_reset_switch()
223 		val.bits.swreset_clkmpc = enable;  in dcgu_set_reset_switch()
226 		val.bits.swreset_clkcve = enable;  in dcgu_set_reset_switch()
229 		val.bits.swreset_clkdvp = enable;  in dcgu_set_reset_switch()
232 		val.bits.swreset_clkmr2 = enable;  in dcgu_set_reset_switch()
235 		val.bits.swreset_clkmr1 = enable;  in dcgu_set_reset_switch()