Lines Matching +full:poll +full:- +full:timeout +full:- +full:ms
5 * Copyright 2007-2011 Freescale Semiconductor, Inc.
7 * SPDX-License-Identifier: GPL-2.0+
36 /* approx 10ms */ in trigger_fpga_config()
37 u32 timeout = 10000; in trigger_fpga_config() local
54 if (timeout-- == 0) { in trigger_fpga_config()
55 printf("FPGA_INIT timeout\n"); in trigger_fpga_config()
56 ret = -EFAULT; in trigger_fpga_config()
68 /* poll the FPGA_DONE signal and give the EEPROM back to the QorIQ */
73 u32 timeout = 500000; in wait_for_fpga_config() local
78 if (timeout-- == 0) { in wait_for_fpga_config()
79 printf(" FPGA_DONE timeout\n"); in wait_for_fpga_config()
80 ret = -EFAULT; in wait_for_fpga_config()