keymile/km_arm/kwbimage.cfg

3 # Heiko Schocher, DENX Software Engineering, hs@denx.de.
5 # SPDX-License-Identifier:	GPL-2.0+
7 # Refer doc/README.kwbimage for more details about how-to configure
15 # bit 3-0:   MPPSel0	2, NF_IO[2]
16 # bit 7-4:   MPPSel1	2, NF_IO[3]
17 # bit 12-8:  MPPSel2	2, NF_IO[4]
18 # bit 15-12: MPPSel3	2, NF_IO[5]
19 # bit 19-16: MPPSel4	1, NF_IO[6]
20 # bit 23-20: MPPSel5	1, NF_IO[7]
21 # bit 27-24: MPPSel6	1, SYSRST_O
22 # bit 31-28: MPPSel7	0, GPO[7]
27 # bit 3-0:   MPPSel16	0, GPIO[16]
28 # bit 7-4:   MPPSel17	0, GPIO[17]
29 # bit 12-8:  MPPSel18	1, NF_IO[0]
30 # bit 15-12: MPPSel19	1, NF_IO[1]
31 # bit 19-16: MPPSel20	0, GPIO[20]
32 # bit 23-20: MPPSel21	0, GPIO[21]
33 # bit 27-24: MPPSel22	0, GPIO[22]
34 # bit 31-28: MPPSel23	0, GPIO[23]
45 # bit13-0:  0x400 (DDR2 clks refresh rate)
46 # bit23-14: zero
49 # bit29-26: zero
50 # bit31-30: 01
53 # bit 3-0:  0 reserved
59 # bit23-20: 3=recommended value for CL=3 and STARTBURST_DEL disabled bit31=0
60 # bit27-24: 6= CL+3, STARTBURST sample stages, for freqs 400MHz, unbuffered DIMM
61 # bit30-28: 3 required
65 # bit3-0:   TRAS lsbs
66 # bit7-4:   TRCD
67 # bit11- 8: TRP
68 # bit15-12: TWR
69 # bit19-16: TWTR
71 # bit23-21: 0x0
72 # bit27-24: TRRD
73 # bit31-28: TRTP
76 # bit6-0:   TRFC
77 # bit8-7:   TR2R
78 # bit10-9:  TR2W
79 # bit12-11: TW2W
80 # bit31-13: zero required
83 # bit1-0:   01, Cs0width=x16
84 # bit3-2:   11, Cs0size=1Gb
85 # bit5-4:   00, Cs2width=nonexistent
86 # bit7-6:   00, Cs1size =nonexistent
87 # bit9-8:   00, Cs2width=nonexistent
88 # bit11-10: 00, Cs2size =nonexistent
89 # bit13-12: 00, Cs3width=nonexistent
90 # bit15-14: 00, Cs3size =nonexistent
95 # bit31-20: 0 required
99 # bit31-1: 0 required
102 # bit3-0:   0x0, DDR cmd
103 # bit31-4:  0 required
110 # bit5-3:  000, required
112 # bit9-7:  000, required
116 # bit31-13: 0 required
119 # bit2-0:  111, required
121 # bit6-4:  111, required
127 # bit15-12: 1111 required
128 # bit31-16: 0    required
136 # bit3-2:  00, CS0 hit selected
137 # bit23-4: ones, required
138 # bit31-24: 0x07, Size (i.e. 128MB)
145 # bit3-0:  0, ODT0Rd, MODT[0] asserted during read from DRAM CS0
146 # bit19-16:0, ODT0Wr, MODT[0] asserted during write to DRAM CS0
149 # bit1-0:  00, ODT0 controlled by ODT Control (low) register above
150 # bit3-2:  00, ODT1 controlled by register
151 # bit31-4: zero, required
154 # bit3-0:  F, ODT0Rd, Internal ODT asserted during read from DRAM bank0
155 # bit7-4:  0, ODT0Wr, Internal ODT asserted during write to DRAM bank0
156 # bit9-8:  1, ODTEn, never active
157 # bit11-10:2, DQ_ODTSel. ODT select turned on, 75 ohm