keymile/km_arm/kwbimage-memphis.cfg

3 # Heiko Schocher, DENX Software Engineering, hs@denx.de.
8 # SPDX-License-Identifier:	GPL-2.0+
10 # Refer doc/README.kwbimage for more details about how-to configure
18 # bit 3-0:   MPPSel0	2, NF_IO[2]
19 # bit 7-4:   MPPSel1	2, NF_IO[3]
20 # bit 12-8:  MPPSel2	2, NF_IO[4]
21 # bit 15-12: MPPSel3	2, NF_IO[5]
22 # bit 19-16: MPPSel4	1, NF_IO[6]
23 # bit 23-20: MPPSel5	1, NF_IO[7]
24 # bit 27-24: MPPSel6	1, SYSRST_O
25 # bit 31-28: MPPSel7	0, GPO[7]
30 # bit 3-0:   MPPSel16	0, GPIO[16]
31 # bit 7-4:   MPPSel17	0, GPIO[17]
32 # bit 12-8:  MPPSel18	1, NF_IO[0]
33 # bit 15-12: MPPSel19	1, NF_IO[1]
34 # bit 19-16: MPPSel20	0, GPIO[20]
35 # bit 23-20: MPPSel21	0, GPIO[21]
36 # bit 27-24: MPPSel22	0, GPIO[22]
37 # bit 31-28: MPPSel23	0, GPIO[23]
48 # bit13-0:  0x4E0 (DDR2 clks refresh rate)
49 # bit23-14: zero
52 # bit29-26: zero
53 # bit31-30: 01
56 # bit 3-0:  0 reserved
62 # bit23-20: 5=recommended value for CL=4 and STARTBURST_DEL disabled bit31=0
63 # bit27-24: 8= CL+4, STARTBURST sample stages, for freqs 400MHz, unbuffered DIMM
64 # bit30-28: 3 required
68 # bit3-0:   TRAS lsbs
69 # bit7-4:   TRCD
70 # bit11- 8: TRP
71 # bit15-12: TWR
72 # bit19-16: TWTR
74 # bit23-21: 0x0
75 # bit27-24: TRRD
76 # bit31-28: TRTP
79 # bit6-0:   TRFC
80 # bit8-7:   TR2R
81 # bit10-9:  TR2W
82 # bit12-11: TW2W
83 # bit31-13: zero required
86 # bit1-0:   01, Cs0width=x16
87 # bit3-2:   00, Cs0size=2Gb
88 # bit5-4:   00, Cs2width=nonexistent
89 # bit7-6:   00, Cs1size =nonexistent
90 # bit9-8:   00, Cs2width=nonexistent
91 # bit11-10: 00, Cs2size =nonexistent
92 # bit13-12: 00, Cs3width=nonexistent
93 # bit15-14: 00, Cs3size =nonexistent
98 # bit31-20: 0 required
102 # bit31-1: 0 required
105 # bit3-0:   0x0, DDR cmd
106 # bit31-4:  0 required
113 # bit5-3:  000, required
115 # bit9-7:  000, required
119 # bit31-13: 0 required
122 # bit2-0:  111, required
124 # bit6-4:  111, required
130 # bit15-12: 1111 required
131 # bit31-16: 0    required
134 # bit3-0  : 0000, required
135 # bit7-4  : 0010, M_ODT assertion 2 cycles after read
136 # bit11-8 : 0101, M_ODT de-assertion 5 cycles after read
137 # bit15-12: 0100, internal ODT assertion 4 cycles after read
138 # bit19-16: 1000, internal ODT de-assertion 8 cycles after read
139 # bit31-20: 0   , required
142 # bit3-0  : 0001, M_ODT assertion same cycle as write
143 # bit7-4  : 0101, M_ODT de-assertion x cycles after write
144 # bit11-8 : 0100, internal ODT assertion x cycles after write
145 # bit15-12: 1000, internal ODT de-assertion x cycles after write
151 # bit3-2:  00, CS0 hit selected
152 # bit23-4: ones, required
153 # bit31-24: 0x0F, Size (i.e. 256MB)
160 # bit3-0:  0, ODT0Rd, MODT[0] not asserted during read from DRAM CS0
161 # bit19-16:1, ODT0Wr, MODT[0] asserted during write to DRAM CS0
164 # bit1-0:  00, ODT0 controlled by ODT Control (low) register above
165 # bit3-2:  00, ODT1 controlled by register
166 # bit31-4: zero, required
169 # bit3-0:  1, ODT0Rd, Internal ODT asserted during read from DRAM bank0
170 # bit7-4:  0, ODT0Wr, Internal ODT not asserted during write to DRAM bank0
171 # bit9-8:  0, ODTEn, controlled by ODT0Rd and ODT0Wr
172 # bit11-10:2, DQ_ODTSel. ODT select turned on, 75 ohm
173 # bit13-12:3, STARTBURST ODT buffer selected, 50 ohm