Lines Matching +full:0 +full:xffd10000
17 DATA 0xFFD10000 0x01112222 # MPP Control 0 Register
18 # bit 3-0: MPPSel0 2, NF_IO[2]
25 # bit 31-28: MPPSel7 0, GPO[7]
27 DATA 0xFFD10004 0x03303300
29 DATA 0xFFD10008 0x00001100 # MPP Control 2 Register
30 # bit 3-0: MPPSel16 0, GPIO[16]
31 # bit 7-4: MPPSel17 0, GPIO[17]
32 # bit 12-8: MPPSel18 1, NF_IO[0]
34 # bit 19-16: MPPSel20 0, GPIO[20]
35 # bit 23-20: MPPSel21 0, GPIO[21]
36 # bit 27-24: MPPSel22 0, GPIO[22]
37 # bit 31-28: MPPSel23 0, GPIO[23]
39 DATA 0xFFD100E0 0x1B1B1B1B # IO Configuration 0 Register
40 DATA 0xFFD20134 0x66666666 # L2 RAM Timing 0 Register
41 DATA 0xFFD20138 0x66666666 # L2 RAM Timing 1 Register
43 # NOTE: Don't write on 0x20148 , 0x2014c and 0x20154, leave them untouched!
47 DATA 0xFFD01400 0x430004E0 # SDRAM Configuration Register
48 # bit13-0: 0x4E0 (DDR2 clks refresh rate)
55 DATA 0xFFD01404 0x38543000 # DDR Controller Control Low
56 # bit 3-0: 0 reserved
57 # bit 4: 0=addr/cmd in smame cycle
58 # bit 5: 0=clk is driven during self refresh, we don't care for APX
59 # bit 6: 0=use recommended falling edge of clk for addr/cmd
60 # bit14: 0=input buffer always powered up
62 # bit23-20: 5=recommended value for CL=4 and STARTBURST_DEL disabled bit31=0
65 # bit31: 0=no additional STARTBURST delay
67 DATA 0xFFD01408 0x2302433E # DDR Timing (Low) (active cycles value +1)
68 # bit3-0: TRAS lsbs
74 # bit23-21: 0x0
78 DATA 0xFFD0140C 0x00000A3E # DDR Timing (High)
79 # bit6-0: TRFC
85 DATA 0xFFD01410 0x00000001 # DDR Address Control
86 # bit1-0: 01, Cs0width=x16
94 # bit16: 0, Cs0AddrSel
95 # bit17: 0, Cs1AddrSel
96 # bit18: 0, Cs2AddrSel
97 # bit19: 0, Cs3AddrSel
98 # bit31-20: 0 required
100 DATA 0xFFD01414 0x00000000 # DDR Open Pages Control
101 # bit0: 0, OpenPage enabled
102 # bit31-1: 0 required
104 DATA 0xFFD01418 0x00000000 # DDR Operation
105 # bit3-0: 0x0, DDR cmd
106 # bit31-4: 0 required
108 DATA 0xFFD0141C 0x00000652 # DDR Mode
109 DATA 0xFFD01420 0x00000006 # DDR Extended Mode
110 # bit0: 0, DDR DLL enabled
114 # bit6: 0, DDR ODT control msb disabled
116 # bit10: 0, differential DQS enabled
117 # bit11: 0, required
118 # bit12: 0, DDR output buffer enabled
119 # bit31-13: 0 required
121 DATA 0xFFD01424 0x0000F17F # DDR Controller Control High
122 # bit2-0: 111, required
125 # bit7 : 0
127 # bit9 : 0 , no half clock cycle addition to dataout
128 # bit10 : 0 , 1/4 clock cycle skew enabled for addr/ctl signals
129 # bit11 : 0 , 1/4 clock cycle skew disabled for write mesh
131 # bit31-16: 0 required
133 DATA 0xFFD01428 0x00084520 # DDR2 SDRAM Timing Low
134 # bit3-0 : 0000, required
139 # bit31-20: 0 , required
141 DATA 0xFFD0147c 0x00008451 # DDR2 SDRAM Timing High
142 # bit3-0 : 0001, M_ODT assertion same cycle as write
147 DATA 0xFFD01500 0x00000000 # CS[0]n Base address to 0x0
148 DATA 0xFFD01504 0x0FFFFFF1 # CS[0]n Size
150 # bit1: 0, Write Protect disabled
153 # bit31-24: 0x0F, Size (i.e. 256MB)
155 DATA 0xFFD0150C 0x00000000 # CS[1]n Size, window disabled
156 DATA 0xFFD01514 0x00000000 # CS[2]n Size, window disabled
157 DATA 0xFFD0151C 0x00000000 # CS[3]n Size, window disabled
159 DATA 0xFFD01494 0x00010000 # DDR ODT Control (Low)
160 # bit3-0: 0, ODT0Rd, MODT[0] not asserted during read from DRAM CS0
161 # bit19-16:1, ODT0Wr, MODT[0] asserted during write to DRAM CS0
163 DATA 0xFFD01498 0x00000000 # DDR ODT Control (High)
164 # bit1-0: 00, ODT0 controlled by ODT Control (low) register above
168 DATA 0xFFD0149C 0x0000F801 # CPU ODT Control
169 # bit3-0: 1, ODT0Rd, Internal ODT asserted during read from DRAM bank0
170 # bit7-4: 0, ODT0Wr, Internal ODT not asserted during write to DRAM bank0
171 # bit9-8: 0, ODTEn, controlled by ODT0Rd and ODT0Wr
177 DATA 0xFFD01480 0x00000001 # DDR Initialization Control
181 DATA 0x0 0x0