Lines Matching refs:t0

32 	PTR_LI	t0, CKSEG1ADDR(MALTA_REVISION)
33 	lw	t0, 0(t0)
34 	srl	t0, t0, MALTA_REVISION_CORID_SHF
35 	andi	t0, t0, (MALTA_REVISION_CORID_MSK >> \
40 	beq	t0, t1, _gt64120
44 	beq	t0, t1, _msc01
67 	li	t0, CPU_TO_GT32(0xdf000000)
68 	sw	t0, GT_ISD_OFS(t1)
74 	li	t0, CPU_TO_GT32(0xc0000000)
75 	sw	t0, GT_PCI0IOLD_OFS(t1)
76 	li	t0, CPU_TO_GT32(0x40000000)
77 	sw	t0, GT_PCI0IOHD_OFS(t1)
80 	li	t0, CPU_TO_GT32(0x80000000)
81 	sw	t0, GT_PCI0M0LD_OFS(t1)
82 	li	t0, CPU_TO_GT32(0x3f000000)
83 	sw	t0, GT_PCI0M0HD_OFS(t1)
85 	li	t0, CPU_TO_GT32(0xc1000000)
86 	sw	t0, GT_PCI0M1LD_OFS(t1)
87 	li	t0, CPU_TO_GT32(0x5e000000)
88 	sw	t0, GT_PCI0M1HD_OFS(t1)
98 	PTR_LI	t0, CKSEG1ADDR(MALTA_MSC01_PBC_BASE)
100 	sw	t1, MSC01_PBC_CLKCFG_OFS(t0)
105 	sw	t1, MSC01_PBC_CS0TIM_OFS(t0)
110 	sw	t1, MSC01_PBC_CS0RW_OFS(t0)
111 	lw	t1, MSC01_PBC_CS0CFG_OFS(t0)
117 	sw	t1, MSC01_PBC_CS0CFG_OFS(t0)
120 	PTR_LI	t0, CKSEG1ADDR(MALTA_MSC01_BIU_BASE)
123 	sw	t1, MSC01_BIU_MCBAS1L_OFS(t0)
124 	sw	t2, MSC01_BIU_MCMSK1L_OFS(t0)
125 	sw	t1, MSC01_BIU_MCBAS2L_OFS(t0)
126 	sw	t2, MSC01_BIU_MCMSK2L_OFS(t0)
131 	sw	t1, MSC01_BIU_IP1BAS1L_OFS(t0)
132 	sw	t2, MSC01_BIU_IP1MSK1L_OFS(t0)
133 	sw	t1, MSC01_BIU_IP1BAS2L_OFS(t0)
134 	sw	t2, MSC01_BIU_IP1MSK2L_OFS(t0)
139 	sw	t1, MSC01_BIU_IP2BAS1L_OFS(t0)
140 	sw	t2, MSC01_BIU_IP2MSK1L_OFS(t0)
143 	sw	t1, MSC01_BIU_IP2BAS2L_OFS(t0)
144 	sw	t2, MSC01_BIU_IP2MSK2L_OFS(t0)
149 	sw	t1, MSC01_BIU_IP3BAS1L_OFS(t0)
150 	sw	t2, MSC01_BIU_IP3MSK1L_OFS(t0)
151 	sw	t1, MSC01_BIU_IP3BAS2L_OFS(t0)
152 	sw	t2, MSC01_BIU_IP3MSK2L_OFS(t0)
155 	PTR_LI	t0, CKSEG1ADDR(MALTA_MSC01_PCI_BASE)
159 	sw	t1, MSC01_PCI_SC2PMBASL_OFS(t0)
160 	sw	t2, MSC01_PCI_SC2PMMSKL_OFS(t0)
161 	sw	t3, MSC01_PCI_SC2PMMAPL_OFS(t0)
167 	sw	t1, MSC01_PCI_SC2PIOBASL_OFS(t0)
168 	sw	t2, MSC01_PCI_SC2PIOMSKL_OFS(t0)
169 	sw	t3, MSC01_PCI_SC2PIOMAPL_OFS(t0)
173 	sw	t1, MSC01_PCI_BAR0_OFS(t0)
176 	sw	t1, MSC01_PCI_P2SCMSKL_OFS(t0)
177 	sw	zero, MSC01_PCI_P2SCMAPL_OFS(t0)
182 	sw	t1, MSC01_PCI_HEAD0_OFS(t0)
185 	sw	t1, MSC01_PCI_HEAD11_OFS(t0)
190 	sw	t1, MSC01_PCI_HEAD2_OFS(t0)
193 	sw	zero, MSC01_PCI_HEAD3_OFS(t0)
194 	sw	zero, MSC01_PCI_HEAD4_OFS(t0)
195 	sw	zero, MSC01_PCI_HEAD5_OFS(t0)
196 	sw	zero, MSC01_PCI_HEAD6_OFS(t0)
197 	sw	zero, MSC01_PCI_HEAD7_OFS(t0)
198 	sw	zero, MSC01_PCI_HEAD8_OFS(t0)
199 	sw	zero, MSC01_PCI_HEAD9_OFS(t0)
200 	sw	zero, MSC01_PCI_HEAD10_OFS(t0)
201 	sw	zero, MSC01_PCI_HEAD12_OFS(t0)
202 	sw	zero, MSC01_PCI_HEAD13_OFS(t0)
203 	sw	zero, MSC01_PCI_HEAD14_OFS(t0)
204 	sw	zero, MSC01_PCI_HEAD15_OFS(t0)
212 	sw	t1, MSC01_PCI_HEAD1_OFS(t0)
218 	sw	t1, MSC01_PCI_SWAP_OFS(t0)
220 	sw	zero, MSC01_PCI_SWAP_OFS(t0)
224 	lw	t1, MSC01_PCI_CFG_OFS(t0)
229 	sw	t1, MSC01_PCI_CFG_OFS(t0)