Lines Matching refs:li
39 li t1, MALTA_REVISION_CORID_CORE_LV
43 li t1, MALTA_REVISION_CORID_CORE_FPGA6
67 li t0, CPU_TO_GT32(0xdf000000)
74 li t0, CPU_TO_GT32(0xc0000000)
76 li t0, CPU_TO_GT32(0x40000000)
80 li t0, CPU_TO_GT32(0x80000000)
82 li t0, CPU_TO_GT32(0x3f000000)
85 li t0, CPU_TO_GT32(0xc1000000)
87 li t0, CPU_TO_GT32(0x5e000000)
99 li t1, 0x1 << MSC01_PBC_CLKCFG_SHF
103 li t1, (0x1 << MSC01_PBC_CS0TIM_CDT_SHF) | \
106 li t1, (0x0 << MSC01_PBC_CS0RW_RDT_SHF) | \
112 li t2, MSC01_PBC_CS0CFG_DTYP_MSK
121 li t1, 0x0
122 li t2, -CONFIG_SYS_MEM_SIZE
129 li t1, MALTA_MSC01_IP1_BASE
130 li t2, -MALTA_MSC01_IP1_SIZE
137 li t1, MALTA_MSC01_IP2_BASE1
138 li t2, -MALTA_MSC01_IP2_SIZE1
141 li t1, MALTA_MSC01_IP2_BASE2
142 li t2, -MALTA_MSC01_IP2_SIZE2
147 li t1, MALTA_MSC01_IP3_BASE
148 li t2, -MALTA_MSC01_IP3_SIZE
156 li t1, MALTA_MSC01_PCIMEM_BASE
157 li t2, (-MALTA_MSC01_PCIMEM_SIZE) & MSC01_PCI_SC2PMMSKL_MSK_MSK
158 li t3, MALTA_MSC01_PCIMEM_MAP
164 li t1, MALTA_MSC01_PCIIO_BASE
165 li t2, (-MALTA_MSC01_PCIIO_SIZE) & MSC01_PCI_SC2PIOMSKL_MSK_MSK
166 li t3, MALTA_MSC01_PCIIO_MAP
172 li t1, -CONFIG_SYS_MEM_SIZE
180 li t1, (PCI_VENDOR_ID_MIPS << MSC01_PCI_HEAD0_VENDORID_SHF) | \
188 li t1, (PCI_CLASS_BRIDGE_HOST << MSC01_PCI_HEAD2_CLASS_SHF) | \
207 li t1, (PCI_COMMAND_FAST_BACK | \
216 li t1, (0x1 << MSC01_PCI_SWAP_BAR0_BSWAP_SHF) | \
225 li t2, MSC01_PCI_CFG_RA_MSK | \