Lines Matching refs:t1
39 li t1, MALTA_REVISION_CORID_CORE_LV
40 beq t0, t1, _gt64120
43 li t1, MALTA_REVISION_CORID_CORE_FPGA6
44 beq t0, t1, _msc01
66 PTR_LI t1, CKSEG1ADDR(GT_DEF_BASE)
68 sw t0, GT_ISD_OFS(t1)
71 PTR_LI t1, CKSEG1ADDR(MALTA_GT_BASE)
75 sw t0, GT_PCI0IOLD_OFS(t1)
77 sw t0, GT_PCI0IOHD_OFS(t1)
81 sw t0, GT_PCI0M0LD_OFS(t1)
83 sw t0, GT_PCI0M0HD_OFS(t1)
86 sw t0, GT_PCI0M1LD_OFS(t1)
88 sw t0, GT_PCI0M1HD_OFS(t1)
99 li t1, 0x1 << MSC01_PBC_CLKCFG_SHF
100 sw t1, MSC01_PBC_CLKCFG_OFS(t0)
103 li t1, (0x1 << MSC01_PBC_CS0TIM_CDT_SHF) | \
105 sw t1, MSC01_PBC_CS0TIM_OFS(t0)
106 li t1, (0x0 << MSC01_PBC_CS0RW_RDT_SHF) | \
110 sw t1, MSC01_PBC_CS0RW_OFS(t0)
111 lw t1, MSC01_PBC_CS0CFG_OFS(t0)
113 and t1, t2
114 ori t1, (0x0 << MSC01_PBC_CS0CFG_ADM_SHF) | \
117 sw t1, MSC01_PBC_CS0CFG_OFS(t0)
121 li t1, 0x0
123 sw t1, MSC01_BIU_MCBAS1L_OFS(t0)
125 sw t1, MSC01_BIU_MCBAS2L_OFS(t0)
129 li t1, MALTA_MSC01_IP1_BASE
131 sw t1, MSC01_BIU_IP1BAS1L_OFS(t0)
133 sw t1, MSC01_BIU_IP1BAS2L_OFS(t0)
137 li t1, MALTA_MSC01_IP2_BASE1
139 sw t1, MSC01_BIU_IP2BAS1L_OFS(t0)
141 li t1, MALTA_MSC01_IP2_BASE2
143 sw t1, MSC01_BIU_IP2BAS2L_OFS(t0)
147 li t1, MALTA_MSC01_IP3_BASE
149 sw t1, MSC01_BIU_IP3BAS1L_OFS(t0)
151 sw t1, MSC01_BIU_IP3BAS2L_OFS(t0)
156 li t1, MALTA_MSC01_PCIMEM_BASE
159 sw t1, MSC01_PCI_SC2PMBASL_OFS(t0)
164 li t1, MALTA_MSC01_PCIIO_BASE
167 sw t1, MSC01_PCI_SC2PIOBASL_OFS(t0)
172 li t1, -CONFIG_SYS_MEM_SIZE
173 sw t1, MSC01_PCI_BAR0_OFS(t0)
176 sw t1, MSC01_PCI_P2SCMSKL_OFS(t0)
180 li t1, (PCI_VENDOR_ID_MIPS << MSC01_PCI_HEAD0_VENDORID_SHF) | \
182 sw t1, MSC01_PCI_HEAD0_OFS(t0)
185 sw t1, MSC01_PCI_HEAD11_OFS(t0)
188 li t1, (PCI_CLASS_BRIDGE_HOST << MSC01_PCI_HEAD2_CLASS_SHF) | \
190 sw t1, MSC01_PCI_HEAD2_OFS(t0)
207 li t1, (PCI_COMMAND_FAST_BACK | \
212 sw t1, MSC01_PCI_HEAD1_OFS(t0)
216 li t1, (0x1 << MSC01_PCI_SWAP_BAR0_BSWAP_SHF) | \
218 sw t1, MSC01_PCI_SWAP_OFS(t0)
224 lw t1, MSC01_PCI_CFG_OFS(t0)
228 or t1, t1, t2
229 sw t1, MSC01_PCI_CFG_OFS(t0)