7  * ids8313.c - ids8313 board support.
12  * SPDX-License-Identifier:	GPL-2.0+
22  * - board type: *pCpld & 0xF0
23  * - hw-revision: *pCpld & 0x0F
24  * - cpld-revision: *pCpld+1
44 	printf("\nInfo:  HW-Rev: %i, CPLD-Rev: %i\n",  in checkboard()
60 	out_be32(&im->sysconf.ddrlaw[0].bar,  in fixed_sdram()
62 	out_be32(&im->sysconf.ddrlaw[0].ar, LBLAWAR_EN | (msize_log2 - 1));  in fixed_sdram()
63 	out_be32(&im->sysconf.ddrcdr, CONFIG_SYS_DDRCDR_VALUE);  in fixed_sdram()
72 	out_be32(&im->ddr.csbnds[0].csbnds, (msize - 1) >> 24);  in fixed_sdram()
73 	out_be32(&im->ddr.cs_config[0], config);  in fixed_sdram()
75 	/* currently we use only one CS, so disable the other banks */  in fixed_sdram()
76 	out_be32(&im->ddr.cs_config[1], 0);  in fixed_sdram()
77 	out_be32(&im->ddr.cs_config[2], 0);  in fixed_sdram()
78 	out_be32(&im->ddr.cs_config[3], 0);  in fixed_sdram()
80 	out_be32(&im->ddr.timing_cfg_3, CONFIG_SYS_DDR_TIMING_3);  in fixed_sdram()
81 	out_be32(&im->ddr.timing_cfg_1, CONFIG_SYS_DDR_TIMING_1);  in fixed_sdram()
82 	out_be32(&im->ddr.timing_cfg_2, CONFIG_SYS_DDR_TIMING_2);  in fixed_sdram()
83 	out_be32(&im->ddr.timing_cfg_0, CONFIG_SYS_DDR_TIMING_0);  in fixed_sdram()
85 	out_be32(&im->ddr.sdram_cfg, CONFIG_SYS_SDRAM_CFG);  in fixed_sdram()
86 	out_be32(&im->ddr.sdram_cfg2, CONFIG_SYS_SDRAM_CFG2);  in fixed_sdram()
88 	out_be32(&im->ddr.sdram_mode, CONFIG_SYS_DDR_MODE);  in fixed_sdram()
89 	out_be32(&im->ddr.sdram_mode2, CONFIG_SYS_DDR_MODE_2);  in fixed_sdram()
91 	out_be32(&im->ddr.sdram_interval, CONFIG_SYS_DDR_INTERVAL);  in fixed_sdram()
92 	out_be32(&im->ddr.sdram_clk_cntl, CONFIG_SYS_DDR_CLK_CNTL);  in fixed_sdram()
97 	setbits_be32(&im->ddr.sdram_cfg, SDRAM_CFG_MEM_EN);  in fixed_sdram()
125 	fsl_lbc_t *lbc = &im->im_lbc;  in dram_init()
128 	if ((in_be32(&im->sysconf.immrbar) & IMMRBAR_BASE_ADDR) != (u32)im)  in dram_init()
129 		return -ENXIO;  in dram_init()
133 	out_be32(&lbc->lbcr, CONFIG_SYS_LBC_LBCR);  in dram_init()
134 	out_be32(&lbc->mrtpr, CONFIG_SYS_LBC_MRTPR);  in dram_init()
137 	gd->ram_size = msize;  in dram_init()
157 /* srp umcr mask for rts */
161 	/*srp*/  in misc_init_r()
162 	duart83xx_t *uart1 = &((immap_t *)CONFIG_SYS_IMMR)->duart[0];  in misc_init_r()
163 	duart83xx_t *uart2 = &((immap_t *)CONFIG_SYS_IMMR)->duart[1];  in misc_init_r()
165 	gpio83xx_t *iopd = &((immap_t *)CONFIG_SYS_IMMR)->gpio[0];  in misc_init_r()
171 	setbits_be32(&iopd->dir, IDSCPLD_SPI_CS_MASK);  in misc_init_r()
172 	/*srp - deactivate rts*/  in misc_init_r()
173 	out_8(&uart1->umcr, IDSUMCR_RTS_MASK);  in misc_init_r()
174 	out_8(&uart2->umcr, IDSUMCR_RTS_MASK);  in misc_init_r()
177 	gd->fdt_blob = (void *)CONFIG_SYS_FLASH_BASE;  in misc_init_r()
193 	gpio83xx_t *iopd = &((immap_t *)CONFIG_SYS_IMMR)->gpio[0];  in spi_cs_activate()
197 	out_8(spi_base, 1 << slave->cs);  in spi_cs_activate()
199 	clrbits_be32(&iopd->dat, IDSCPLD_SPI_CS_MASK);  in spi_cs_activate()
204 	gpio83xx_t *iopd = &((immap_t *)CONFIG_SYS_IMMR)->gpio[0];  in spi_cs_deactivate()
208 	out_8(spi_base, 1 << slave->cs);  in spi_cs_deactivate()
210 	setbits_be32(&iopd->dat, IDSCPLD_SPI_CS_MASK);  in spi_cs_deactivate()