11 #define CPHY_MAP(dev, addr) ((((dev) & 0x1f) << 7) | (((addr) >> 9) & 0x7f))
12 #define CPHY_ADDR(base, dev, addr) ((base) | (((addr) & 0x1ff) << 2))
13 #define CPHY_BASE			0xfff58000
14 #define CPHY_WIDTH			0x1000
17 #define SERDES_CR_CTL			0x80a0
18 #define SERDES_CR_ADDR			0x80a1
19 #define SERDES_CR_DATA			0x80a2
20 #define CR_BUSY				0x0001
21 #define CR_START			0x0001
22 #define CR_WR_RDN			0x0002
23 #define CPHY_TX_INPUT_STS		0x2001
24 #define CPHY_RX_INPUT_STS		0x2002
25 #define CPHY_SATA_TX_OVERRIDE_BIT	0x8000
26 #define CPHY_SATA_RX_OVERRIDE_BIT	0x4000
27 #define CPHY_TX_INPUT_OVERRIDE		0x2004
28 #define CPHY_RX_INPUT_OVERRIDE		0x2005
29 #define SPHY_LANE			0x100
30 #define SPHY_HALF_RATE			0x0001
31 #define CPHY_SATA_DPLL_MODE		0x0700
33 #define CPHY_SATA_TX_ATTEN		0x1c00
36 #define HB_SREG_SATA_ATTEN		0xfff3cf24
38 #define SATA_PORT_BASE			0xffe08000
39 #define SATA_VERSIONR			0xf8
40 #define SATA_HB_VERSION			0x3332302a
45 	writel(CPHY_MAP(dev, addr), CPHY_BASE + 0x800 + CPHY_WIDTH * phy);  in __combo_phy_reg_read()
52 	writel(CPHY_MAP(dev, addr), CPHY_BASE + 0x800 + CPHY_WIDTH * phy);  in __combo_phy_reg_write()
105 	val = (readl(HB_SREG_SATA_ATTEN) >> shift) & 0xf;  in cphy_tx_attenuation_override()
107 	if (val & 0x8)  in cphy_tx_attenuation_override()
124 	u8 lane = 0, phy = 0;  in cphy_disable_port_overrides()
126 	if (port == 0)  in cphy_disable_port_overrides()
146 	port_map = readl(0xffe08000 + HOST_PORTS_IMPL);  in cphy_disable_overrides()
147 	for (i = 0; i < 5; i++) {  in cphy_disable_overrides()
155 	u32 tmp, k = 0;  in cphy_override_lane()
156 	u8 lane = 0, phy = 0;  in cphy_override_lane()
158 	if (port == 0)  in cphy_override_lane()
166 		tmp = combo_phy_read(0, CPHY_RX_INPUT_STS +  in cphy_override_lane()
178 	int j = 0;  in ahci_link_up()
181 				SATA_HB_VERSION ? 1 : 0;  in ahci_link_up()
188 		if (is_highbank && (j == 0)) {  in ahci_link_up()
190 			writel(0x301, port_mmio + PORT_SCR_CTL);  in ahci_link_up()
192 			writel(0x300, port_mmio + PORT_SCR_CTL);  in ahci_link_up()
198 		if ((tmp & 0xf) == 0x3)  in ahci_link_up()
199 			return 0;  in ahci_link_up()
203 		if ((j == WAIT_MS_LINKUP) && (tmp & 0xf))  in ahci_link_up()
204 			j = 0;	/* retry phy reset */  in ahci_link_up()