50 	HWVER_100 = 0,
56 	u32 reflection_low;	/* 0x0000 */
57 	u32 versions;		/* 0x0004 */
58 	u32 fpga_version;	/* 0x0008 */
59 	u32 fpga_features;	/* 0x000c */
60 	u32 reserved[4];	/* 0x0010 */
61 	u32 control;		/* 0x0020 */
66 	{ 0x6d5e, 0xcdc0 },
79 	clrsetbits_be32(&gur->pmuxcr, 0x00600000, 0x80000000);  in board_early_init_f()
82 	setbits_be32(&gur->pmuxcr, 0x00001000);  in board_early_init_f()
85 	setbits_be32(&gur->pmuxcr, 0x00000010);  in board_early_init_f()
88 	setbits_be32(&gur->pmuxcr, 0x00000020);  in board_early_init_f()
91 	setbits_be32(&gur->pmuxcr, 0x000000c0);  in board_early_init_f()
94 	setbits_be32(&gur->pmuxcr2, 0x03000000);  in board_early_init_f()
97 	clrbits_be32(&gur->pmuxcr, 0x00000300);  in board_early_init_f()
100 	setbits_be32(&gur->pmuxcr, 0x000000F0);  in board_early_init_f()
106 	clrbits_be32(&gur->pmuxcr2, 0x001F8000);  in board_early_init_f()
112 	setbits_be32(&pgpio->gpdir, 0x00200000);  in board_early_init_f()
113 	clrbits_be32(&pgpio->gpdat, 0x00200000);  in board_early_init_f()
115 	setbits_be32(&pgpio->gpdat, 0x00200000);  in board_early_init_f()
117 	clrbits_be32(&pgpio->gpdat, 0x00200000);  in board_early_init_f()
123 	setbits_be32(&pgpio->gpdir, 0x00100000);  in board_early_init_f()
124 	clrbits_be32(&pgpio->gpdat, 0x00100000);  in board_early_init_f()
129 	setbits_be32(&pgpio->gpdir, 0x00000400);  in board_early_init_f()
131 	return 0;  in board_early_init_f()
138 	return 0;  in checkboard()
143 	return 0;  in misc_init_r()
177 	[0x01] = { [PCIE3] = SLOT_PCIE4, [PCIE2] = SLOT_PCIE5 },
178 	[0x02] = { [SATA1] = SLOT_SATA1, [SATA2] = SLOT_SATA2 },
179 	[0x09] = { [PCIE1] = SLOT_PCIE1, [PCIE3] = SLOT_PCIE4,
181 	[0x16] = { [PCIE1] = SLOT_PCIE1, [PCIE3] = SLOT_PCIE2,
184 	[0x17] = { [PCIE1] = SLOT_PCIE1, [PCIE3] = SLOT_PCIE2,
186 	[0x1a] = { [PCIE1] = SLOT_PCIE1, [PCIE2] = SLOT_PCIE3,
189 	[0x1c] = { [PCIE1] = SLOT_PCIE1,
191 	[0x1e] = { [PCIE1] = SLOT_PCIE1, [PCIE3] = SLOT_PCIE3 },
192 	[0x1f] = { [PCIE1] = SLOT_PCIE1 },
219 	clrbits_be32(&pgpio->gpdat, 0x00000400);  in hw_watchdog_reset()
220 	setbits_be32(&pgpio->gpdat, 0x00000400);  in hw_watchdog_reset()
236 	setbits_be32(&pgpio->gpdir, 0x00080000);  in board_early_init_r()
237 	setbits_be32(&pgpio->gpodr, 0x00080000);  in board_early_init_r()
238 	clrbits_be32(&pgpio->gpdat, 0x00080000);  in board_early_init_r()
246 	return 0;  in last_stage_init()
252 	fsl_pcie_init_board(0);  in pci_init_board()
259 	unsigned int k = 0;  in board_early_init_r()
263 	while (!pca9698_get_value(0x22, 11) && (k++ < 30))  in board_early_init_r()
271 		setbits_be32(&pgpio->gpdat, 0x00100000);  in board_early_init_r()
280 	setbits_be32(&pgpio->gpdir, 0x00080000);  in board_early_init_r()
281 	setbits_be32(&pgpio->gpodr, 0x00080000);  in board_early_init_r()
282 	clrbits_be32(&pgpio->gpdat, 0x00080000);  in board_early_init_r()
284 	return 0;  in board_early_init_r()
290 	pca9698_direction_output(0x22, 7, 1);  in last_stage_init()
293 	dp501_powerup(0x08);  in last_stage_init()
297 	return 0;  in last_stage_init()
304  *      <0, error
305  *       0, no ethernet devices found
306  *      >0, number of ethernet devices initialized
312 	unsigned int num = 0;  in board_eth_init()
349 	return 0;  in ft_board_setup()
359 	for (i = 0; (devno = pci_find_devices(hydra_supported, i)) >= 0; i++) {  in hydra_initialize()
396 		hardware_version = versions & 0xf;  in hydra_initialize()
397 		feature_uart_channels = (fpga_features >> 6) & 0x1f;  in hydra_initialize()
398 		feature_sb_channels = fpga_features & 0x1f;  in hydra_initialize()