26 #define ETH_PHY_CTRL_REG		0
30 #define DB_GP_88F68XX_GPP_OUT_ENA_LOW	0x7fffffff
31 #define DB_GP_88F68XX_GPP_OUT_ENA_MID	0xffffefff
33 #define DB_GP_88F68XX_GPP_OUT_VAL_LOW	0x0
34 #define DB_GP_88F68XX_GPP_OUT_VAL_MID	0x00001000
35 #define DB_GP_88F68XX_GPP_POL_LOW	0x0
36 #define DB_GP_88F68XX_GPP_POL_MID	0x0
44 	0x1, /* active interfaces */
46 	{ { { {0x1, 0, 0, 0},
47 	      {0x1, 0, 0, 0},
48 	      {0x1, 0, 0, 0},
49 	      {0x1, 0, 0, 0},
50 	      {0x1, 0, 0, 0} },
55 	    0, 0,			/* cas_l cas_wl */
63 	{SGMII0, SERDES_SPEED_1_25_GBPS, SERDES_DEFAULT_MODE, 0, 0},
64 	{USB3_HOST0, SERDES_SPEED_5_GBPS, SERDES_DEFAULT_MODE, 0, 0},
66 	{SATA1, SERDES_SPEED_3_GBPS, SERDES_DEFAULT_MODE, 0, 1},
67 	{SGMII2, SERDES_SPEED_1_25_GBPS, SERDES_DEFAULT_MODE, 0, 0},
68 	{DEFAULT_SERDES, SERDES_SPEED_3_GBPS, SERDES_DEFAULT_MODE, 0, 0},
69 	{PEX2, SERDES_SPEED_5_GBPS, PEX_ROOT_COMPLEX_X1, 0, 0}
76 	return 0;  in hws_board_topology_load()
88 		dm_gpio_set_value(&gpio, 0);  in board_pex_config()
99 		for (k = 0; k < 20; ++k) {  in board_pex_config()
116 		for (k = 0; k < 2; ++k) {  in board_pex_config()
134 	writel(0x00111111, MVEBU_MPP_BASE + 0x00);  in board_early_init_f()
135 	writel(0x40040000, MVEBU_MPP_BASE + 0x04);  in board_early_init_f()
136 	writel(0x00466444, MVEBU_MPP_BASE + 0x08);  in board_early_init_f()
137 	writel(0x00043300, MVEBU_MPP_BASE + 0x0c);  in board_early_init_f()
138 	writel(0x44400000, MVEBU_MPP_BASE + 0x10);  in board_early_init_f()
139 	writel(0x20000334, MVEBU_MPP_BASE + 0x14);  in board_early_init_f()
140 	writel(0x40000000, MVEBU_MPP_BASE + 0x18);  in board_early_init_f()
141 	writel(0x00004444, MVEBU_MPP_BASE + 0x1c);  in board_early_init_f()
144 	writel(DB_GP_88F68XX_GPP_OUT_VAL_LOW, MVEBU_GPIO0_BASE + 0x00);  in board_early_init_f()
145 	writel(DB_GP_88F68XX_GPP_OUT_VAL_MID, MVEBU_GPIO1_BASE + 0x00);  in board_early_init_f()
148 	writel(DB_GP_88F68XX_GPP_POL_LOW, MVEBU_GPIO0_BASE + 0x0c);  in board_early_init_f()
149 	writel(DB_GP_88F68XX_GPP_POL_MID, MVEBU_GPIO1_BASE + 0x0c);  in board_early_init_f()
152 	writel(DB_GP_88F68XX_GPP_OUT_ENA_LOW, MVEBU_GPIO0_BASE + 0x04);  in board_early_init_f()
153 	writel(DB_GP_88F68XX_GPP_OUT_ENA_MID, MVEBU_GPIO1_BASE + 0x04);  in board_early_init_f()
156 	return 0;  in board_early_init_f()
162 	gd->bd->bi_boot_params = mvebu_sdram_bar(0) + 0x100;  in board_init()
164 	return 0;  in board_init()
172 	for (k = 0; k < 2; ++k) {  in init_host_phys()
186 	uint octo_phy_mask = 0;  in ccdc_eth_init()
219 	for (k = 0; k < 80; ++k)  in ccdc_eth_init()
224 	for (k = 0; k < 80; ++k)  in ccdc_eth_init()
225 		writel(0, get_fpga()->qsgmii_port_state[k]);  in ccdc_eth_init()
226 	return 0;  in ccdc_eth_init()
236 	return 0;  in board_late_init()
253 	for (k = 0x21; k <= 0x26; k++) {  in board_fix_fdt()
261 	return 0;  in board_fix_fdt()
279 	return 0;  in last_stage_init()