4  * SPDX-License-Identifier:	GPL-2.0+
9 #include <asm/arch/imx-regs.h>
10 #include <asm/arch/iomux-vf610.h>
11 #include <asm/arch/ddrmc-vf610.h>
18 #include <i2c.h>
83 	{ 0, -1 }
142 	gd->ram_size = get_ram_size((void *)PHYS_SDRAM, PHYS_SDRAM_SIZE);  in dram_init()
274 	clrsetbits_le32(&ccm->ccgr0, CCM_REG_CTRL_MASK,  in clock_init()
276 	clrsetbits_le32(&ccm->ccgr1, CCM_REG_CTRL_MASK,  in clock_init()
278 	clrsetbits_le32(&ccm->ccgr2, CCM_REG_CTRL_MASK,  in clock_init()
283 	clrsetbits_le32(&ccm->ccgr3, CCM_REG_CTRL_MASK,  in clock_init()
285 	clrsetbits_le32(&ccm->ccgr4, CCM_REG_CTRL_MASK,  in clock_init()
288 	clrsetbits_le32(&ccm->ccgr6, CCM_REG_CTRL_MASK,  in clock_init()
290 	clrsetbits_le32(&ccm->ccgr7, CCM_REG_CTRL_MASK,  in clock_init()
292 	clrsetbits_le32(&ccm->ccgr9, CCM_REG_CTRL_MASK,  in clock_init()
294 	clrsetbits_le32(&ccm->ccgr10, CCM_REG_CTRL_MASK,  in clock_init()
297 	clrsetbits_le32(&anadig->pll2_ctrl, ANADIG_PLL2_CTRL_POWERDOWN,  in clock_init()
299 	clrsetbits_le32(&anadig->pll1_ctrl, ANADIG_PLL1_CTRL_POWERDOWN,  in clock_init()
302 	clrsetbits_le32(&ccm->ccr, CCM_CCR_OSCNT_MASK,  in clock_init()
304 	clrsetbits_le32(&ccm->ccsr, CCM_REG_CTRL_MASK,  in clock_init()
311 	clrsetbits_le32(&ccm->cacrr, CCM_REG_CTRL_MASK,  in clock_init()
314 	clrsetbits_le32(&ccm->cscmr1, CCM_REG_CTRL_MASK,  in clock_init()
317 	clrsetbits_le32(&ccm->cscdr1, CCM_REG_CTRL_MASK,  in clock_init()
319 	clrsetbits_le32(&ccm->cscdr2, CCM_REG_CTRL_MASK,  in clock_init()
322 	clrsetbits_le32(&ccm->cscdr3, CCM_REG_CTRL_MASK,  in clock_init()
326 	clrsetbits_le32(&ccm->cscmr2, CCM_REG_CTRL_MASK,  in clock_init()
336 		writew(MSCM_IRSPRC_CP0_EN, &mscmir->irsprc[i]);  in mscm_init()
341 	if (phydev->drv->config)  in board_phy_config()
342 		phydev->drv->config(phydev);  in board_phy_config()
368 	gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;  in board_init()
377 	setbits_le32(&scsc->sosc_ctr, SCSC_SOSC_CTR_SOSC_EN);  in board_init()