345 	int i;  in fdt_fixup_board_enet()  local
350 	for (i = FM1_DTSEC1; i < NUM_FM_PORTS; i++) {  in fdt_fixup_board_enet()
351 		switch (fm_info_get_enet_if(i)) {  in fdt_fixup_board_enet()
354 			switch (mdio_mux[i]) {  in fdt_fixup_board_enet()
374 				if (i == FM1_10GEC1 && hwconfig_sub(  in fdt_fixup_board_enet()
378 				if (i == FM1_10GEC2 && hwconfig_sub(  in fdt_fixup_board_enet()
382 				if (i == FM2_10GEC1 && hwconfig_sub(  in fdt_fixup_board_enet()
386 				if (i == FM2_10GEC2 && hwconfig_sub(  in fdt_fixup_board_enet()
392 			switch (i) {  in fdt_fixup_board_enet()
417 	int i;  in initialize_qsgmiiphy_fix()  local
420 	for (i = 1; i <= 4; i++) {  in initialize_qsgmiiphy_fix()
427 		if (miiphy_read(mdio_names[i],  in initialize_qsgmiiphy_fix()
429 			debug("Slot%d PHY ID register 2 read failed\n", i);  in initialize_qsgmiiphy_fix()
433 		debug("Slot%d MII_PHYSID2 @ 0x1c= 0x%04x\n", i, reg);  in initialize_qsgmiiphy_fix()
440 		switch (i) {  in initialize_qsgmiiphy_fix()
490 	int i, idx, lane, slot, interface;  in board_eth_init()  local
504 	for (i = 0; i < NUM_FM_PORTS; i++)  in board_eth_init()
505 		mdio_mux[i] = EMI_NONE;  in board_eth_init()
599 	for (i = FM1_DTSEC1; i < FM1_DTSEC1 + CONFIG_SYS_NUM_FM1_DTSEC; i++) {  in board_eth_init()
600 		idx = i - FM1_DTSEC1;  in board_eth_init()
601 		interface = fm_info_get_enet_if(i);  in board_eth_init()
627 				fm_disable_port(i);  in board_eth_init()
630 				mdio_mux[i] = EMI1_SLOT1;  in board_eth_init()
631 				fm_info_set_mdio(i,  in board_eth_init()
632 					mii_dev_for_muxval(mdio_mux[i]));  in board_eth_init()
635 				mdio_mux[i] = EMI1_SLOT2;  in board_eth_init()
636 				fm_info_set_mdio(i,  in board_eth_init()
637 					mii_dev_for_muxval(mdio_mux[i]));  in board_eth_init()
645 			if (i == FM1_DTSEC5)  in board_eth_init()
646 				fm_info_set_phy_address(i, 2);  in board_eth_init()
647 			mdio_mux[i] = EMI1_RGMII;  in board_eth_init()
648 			fm_info_set_mdio(i,  in board_eth_init()
649 				mii_dev_for_muxval(mdio_mux[i]));  in board_eth_init()
656 	for (i = FM1_10GEC1; i < FM1_10GEC1 + CONFIG_SYS_NUM_FM1_10GEC; i++) {  in board_eth_init()
657 		idx = i - FM1_10GEC1;  in board_eth_init()
658 		switch (fm_info_get_enet_if(i)) {  in board_eth_init()
662 				fm_info_set_phy_address(i, i);  in board_eth_init()
670 					fm_disable_port(i);  in board_eth_init()
672 			mdio_mux[i] = EMI2;  in board_eth_init()
673 			fm_info_set_mdio(i, mii_dev_for_muxval(mdio_mux[i]));  in board_eth_init()
777 	for (i = FM2_DTSEC1; i < FM2_DTSEC1 + CONFIG_SYS_NUM_FM2_DTSEC; i++) {  in board_eth_init()
778 		idx = i - FM2_DTSEC1;  in board_eth_init()
779 		interface = fm_info_get_enet_if(i);  in board_eth_init()
805 				fm_disable_port(i);  in board_eth_init()
808 				mdio_mux[i] = EMI1_SLOT3;  in board_eth_init()
809 				fm_info_set_mdio(i,  in board_eth_init()
810 					mii_dev_for_muxval(mdio_mux[i]));  in board_eth_init()
813 				mdio_mux[i] = EMI1_SLOT4;  in board_eth_init()
814 				fm_info_set_mdio(i,  in board_eth_init()
815 					mii_dev_for_muxval(mdio_mux[i]));  in board_eth_init()
827 				idx + 1, i == FM2_DTSEC5 ? 1 : 2);  in board_eth_init()
828 			fm_info_set_phy_address(i, i == FM2_DTSEC5 ? 1 : 2);  in board_eth_init()
829 			mdio_mux[i] = EMI1_RGMII;  in board_eth_init()
830 			fm_info_set_mdio(i, mii_dev_for_muxval(mdio_mux[i]));  in board_eth_init()
837 	for (i = FM2_10GEC1; i < FM2_10GEC1 + CONFIG_SYS_NUM_FM2_10GEC; i++) {  in board_eth_init()
838 		idx = i - FM2_10GEC1;  in board_eth_init()
839 		switch (fm_info_get_enet_if(i)) {  in board_eth_init()
843 				fm_info_set_phy_address(i, i);  in board_eth_init()
851 					fm_disable_port(i);  in board_eth_init()
853 			mdio_mux[i] = EMI2;  in board_eth_init()
854 			fm_info_set_mdio(i, mii_dev_for_muxval(mdio_mux[i]));  in board_eth_init()