Lines Matching +full:high +full:- +full:side
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3 The T4240QDS is a high-performance computing evaluation, development and test
5 optimized to support the high-bandwidth DDR3 memory ports, as well as the
6 highly-configurable SerDes ports. The system is lead-free and RoHS-compliant.
10 32 lanes grouped into four 8-lane banks
11 Two “front side” banks dedicated to Ethernet
12 - High-speed crosspoint switch fabric on selected lanes
13 - Two PCI Express slots with side-band connector supporting
14 - SGMII
15 - XAUI
16 - HiGig
17 - I-pass connectors allow board-to-board and loopback support
18 Two “back side” banks dedicated to other protocols
19 - High-speed crosspoint switch fabric on all lanes
20 - Four PCI Express slots with side-band connector supporting
21 - PCI Express 3.0
22 - SATA 2.0
23 - SRIO 2.0
24 - Supports 4X Aurora debug with two connectors
26 Three independant 64-bit DDR3 controllers
27 Supports rates of 1866 up to 2133 MHz data-rate
30 Power software-switchable to 1.35V if software detects all DDR3LP devices.
31 MT9JSF25672AZ-2G1KZESZF has been tested at 1333, 1600, 1867, 2000 and
32 2133MT/s speeds. For 1867MT/s and above, read-to-write turnaround time
36 NAND flash: 8-bit, async or sync, up to 2GB.
37 NOR: 16-bit, Address/Data Multiplexed (ADM), up to 128 MB
38 NOR: 8-bit or 16-bit, non-multiplexed, up to 512MB
39 - NOR devices support 16 virtual banks
43 - Flexible demux allows 8 or 16 bit evaluation.
45 - Support for 32-bit devices
47 Support two on-board RGMII 10/100/1G ethernet ports.
53 Collects V-I-T data in background for code/power profiling.
54 Supports legacy TMT test features (POSt, IRS, SYSCLK-synchronous assertion)
59 - Switch selectable to one of 16 common settings in the interval 33MHz-166MHz.
60 - Software selectable in 1MHz increments from 1-200MHz.
62 - Provides clocks to all SerDes blocks and slots
63 - 100, 125 and 156.25 MHz
66 - Adjustable from (0.7V to 1.3V at 80A
67 - Regulators can be controlled by VID and/or software
69 - VTT/MVREF automatically track operating voltage
74 - One type A, one type micro-AB with 1.0A power per port.
77 - SDHC card slot
79 - High-speed serial flash
83 XFI is supported on T4QDS-XFI board which removed slot3 and routed
86 10GBASE-KR scenario.
89 introduced to indicate a XFI port will use copper cable, and U-Boot
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106 0x0_0000_0000 (0x0_0000_0000) - 0x0_7fff_ffff 2GB DDR (more than 2GB is initialized but not mappe…
107 0x0_8000_0000 (0xc_0000_0000) - 0x0_dfff_ffff 1.5GB PCIE memory
108 0x0_f000_0000 (0xf_0000_0000) - 0x0_f1ff_ffff 32MB DCSR (includes trace buffers)
109 0x0_f400_0000 (0xf_f400_0000) - 0x0_f5ff_ffff 32MB BMan
110 0x0_f600_0000 (0xf_f600_0000) - 0x0_f7ff_ffff 32MB QMan
111 0x0_f800_0000 (0xf_f800_0000) - 0x0_f803_ffff 256KB PCIE IO
112 0x0_e000_0000 (0xf_e000_0000) - 0x0_efff_ffff 256MB NOR flash
113 0x0_fe00_0000 (0xf_fe00_0000) - 0x0_feff_ffff 16MB CCSR
114 0x0_ffdf_0000 (0xf_ffdf_0000) - 0x0_ffdf_03ff 4KB QIXIS
115 0x0_ffff_f000 (0x0_7fff_fff0) - 0x0_ffff_ffff 4KB Boot page translation for secondary cores
120 --------------------
121 T4240 has a VID feature. U-Boot reads the VID efuses and adjust the voltage
143 2-stage NAND/SD boot loader
144 -------------------------------
147 and copy U-Boot(768 KB) from NAND/SD device to DDR.
148 Finally SPL transers control to U-Boot for futher booting.
151 - Executes within 256K
152 - No relocation required
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167 -------------------------------------------------
168 |U-Boot SPL | 0xFFFD8000 (160KB) |
169 -------------------------------------------------
172 --------------------------------------------------------------
174 0x000000 0x0FFFFF U-Boot img 1MB
175 0x140000 0x15FFFF U-Boot env 128KB
179 ----------------------------------------------------
181 0x008 2048 U-Boot img 1MB
182 0x800 0016 U-Boot env 8KB