Lines Matching +full:0 +full:xfff00000
14 /* TLB 0 - for temp stack in cache */
15 SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR,
17 MAS3_SX|MAS3_SW|MAS3_SR, 0,
18 0, 0, BOOKE_PAGESZ_4K, 0),
19 SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024,
21 MAS3_SX|MAS3_SW|MAS3_SR, 0,
22 0, 0, BOOKE_PAGESZ_4K, 0),
23 SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024,
25 MAS3_SX|MAS3_SW|MAS3_SR, 0,
26 0, 0, BOOKE_PAGESZ_4K, 0),
27 SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024,
29 MAS3_SX|MAS3_SW|MAS3_SR, 0,
30 0, 0, BOOKE_PAGESZ_4K, 0),
37 * SRAM is at 0xfff00000, it covered the 0xfffff000.
41 0, 0, BOOKE_PAGESZ_1M, 1),
45 * space is at 0xfff00000, it covered the 0xfffff000.
50 0, 0, BOOKE_PAGESZ_1M, 1),
52 SET_TLB_ENTRY(1, 0xfffff000, 0xfffff000,
54 0, 0, BOOKE_PAGESZ_4K, 1),
60 0, 1, BOOKE_PAGESZ_16M, 1),
66 0, 2, BOOKE_PAGESZ_256M, 1),
69 /* *I*G* - PCIe 1, 0x80000000 */
72 0, 3, BOOKE_PAGESZ_512M, 1),
74 /* *I*G* - PCIe 2, 0xa0000000 */
77 0, 4, BOOKE_PAGESZ_256M, 1),
79 /* *I*G* - PCIe 3, 0xb0000000 */
82 0, 5, BOOKE_PAGESZ_256M, 1),
85 /* *I*G* - PCIe 4, 0xc0000000 */
88 0, 6, BOOKE_PAGESZ_256M, 1),
93 0, 7, BOOKE_PAGESZ_256K, 1),
98 MAS3_SX|MAS3_SW|MAS3_SR, 0,
99 0, 9, BOOKE_PAGESZ_16M, 1),
100 SET_TLB_ENTRY(1, CONFIG_SYS_BMAN_MEM_BASE + 0x01000000,
101 CONFIG_SYS_BMAN_MEM_PHYS + 0x01000000,
103 0, 10, BOOKE_PAGESZ_16M, 1),
107 MAS3_SX|MAS3_SW|MAS3_SR, 0,
108 0, 11, BOOKE_PAGESZ_16M, 1),
109 SET_TLB_ENTRY(1, CONFIG_SYS_QMAN_MEM_BASE + 0x01000000,
110 CONFIG_SYS_QMAN_MEM_PHYS + 0x01000000,
112 0, 12, BOOKE_PAGESZ_16M, 1),
118 0, 13, BOOKE_PAGESZ_32M, 1),
128 0, 16, BOOKE_PAGESZ_64K, 1),
133 0, 17, BOOKE_PAGESZ_4K, 1),
137 * SRIO_PCIE_BOOT-SLAVE. 1M space from 0xffe00000 for
143 0, 18, BOOKE_PAGESZ_1M, 1),
147 MAS3_SX|MAS3_SW|MAS3_SR, 0,
148 0, 19, BOOKE_PAGESZ_2G, 1)