Lines Matching full:sd1
116 /* SD1(A:D) => SLOT3 SGMII in brd_mux_lane_to_slot()
117 * SD1(G:H) => SLOT1 SGMII in brd_mux_lane_to_slot()
123 /* SD1(A:B) => SLOT3 SGMII@1.25bps in brd_mux_lane_to_slot()
124 * SD1(C:D) => SFP Module, SGMII@3.125bps in brd_mux_lane_to_slot()
125 * SD1(E:H) => SLOT1 SGMII@1.25bps in brd_mux_lane_to_slot()
128 /* SD1(A:B) => SLOT3 SGMII@1.25bps in brd_mux_lane_to_slot()
129 * SD1(C) => SFP Module, SGMII@3.125bps in brd_mux_lane_to_slot()
130 * SD1(D) => SFP Module, SGMII@1.25bps in brd_mux_lane_to_slot()
131 * SD1(E:H) => SLOT1 PCIe4 x4 in brd_mux_lane_to_slot()
137 /* SD1(A:D) => SLOT3 XAUI in brd_mux_lane_to_slot()
138 * SD1(E) => SLOT1 PCIe4 in brd_mux_lane_to_slot()
139 * SD1(F:H) => SLOT2 SGMII in brd_mux_lane_to_slot()
145 /* SD1(A:D) => XFI cage in brd_mux_lane_to_slot()
146 * SD1(E:H) => SLOT1 PCIe4 in brd_mux_lane_to_slot()
152 /* SD1(A:D) => XFI cage in brd_mux_lane_to_slot()
153 * SD1(E) => SLOT1 PCIe4 in brd_mux_lane_to_slot()
154 * SD1(F:H) => SLOT2 SGMII in brd_mux_lane_to_slot()
160 /* SD1(A:B) => XFI cage in brd_mux_lane_to_slot()
161 * SD1(C:D) => SLOT3 SGMII in brd_mux_lane_to_slot()
162 * SD1(E:H) => SLOT1 PCIe4 in brd_mux_lane_to_slot()
167 /* SD1(A:B) => SFP Module, XFI in brd_mux_lane_to_slot()
168 * SD1(C:D) => SLOT3 SGMII in brd_mux_lane_to_slot()
169 * SD1(E:F) => SLOT1 PCIe4 x2 in brd_mux_lane_to_slot()
170 * SD1(G:H) => SLOT2 SGMII in brd_mux_lane_to_slot()
175 /* SD1(A:H) => SLOT3 PCIe3 x8 in brd_mux_lane_to_slot()
180 /* SD1(A) => SLOT3 PCIe3 x1 in brd_mux_lane_to_slot()
181 * SD1(B) => SFP Module, SGMII@1.25bps in brd_mux_lane_to_slot()
182 * SD1(C:D) => SFP Module, SGMII@3.125bps in brd_mux_lane_to_slot()
183 * SD1(E:F) => SLOT1 PCIe4 x2 in brd_mux_lane_to_slot()
184 * SD1(G:H) => SLOT2 SGMII in brd_mux_lane_to_slot()
189 /* SD1(A:D) => SLOT3 PCIe3 x4 in brd_mux_lane_to_slot()
190 * SD1(E:H) => SLOT1 PCIe4 x4 in brd_mux_lane_to_slot()
197 /* SD1(A:D) => SLOT2 XAUI in brd_mux_lane_to_slot()
198 * SD1(E) => SLOT1 PCIe4 x1 in brd_mux_lane_to_slot()
199 * SD1(F:H) => SLOT3 SGMII in brd_mux_lane_to_slot()
206 /* SD1(A:D) => XFI SFP Module in brd_mux_lane_to_slot()
207 * SD1(E) => SLOT1 PCIe4 x1 in brd_mux_lane_to_slot()
208 * SD1(F:H) => SLOT3 SGMII in brd_mux_lane_to_slot()
215 /* SD1(A:B) => XFI SFP Module in brd_mux_lane_to_slot()
216 * SD1(C:D) => SLOT2 SGMII in brd_mux_lane_to_slot()
217 * SD1(E:H) => SLOT1 PCIe4 x4 in brd_mux_lane_to_slot()
224 /* SD1(A:D) => SLOT2 PCIe3 x4 in brd_mux_lane_to_slot()
225 * SD1(F:H) => SLOT1 SGMI4 x4 in brd_mux_lane_to_slot()
232 /* SD1(A) => SLOT2 PCIe3 x1 in brd_mux_lane_to_slot()
233 * SD1(B) => SLOT7 SGMII in brd_mux_lane_to_slot()
234 * SD1(C) => SLOT6 SGMII in brd_mux_lane_to_slot()
235 * SD1(D) => SLOT5 SGMII in brd_mux_lane_to_slot()
236 * SD1(E) => SLOT1 PCIe4 x1 in brd_mux_lane_to_slot()
237 * SD1(F:H) => SLOT3 SGMII in brd_mux_lane_to_slot()
244 /* SD1(A:D) => SLOT2 PCIe3 x4 in brd_mux_lane_to_slot()
245 * SD1(E) => SLOT1 PCIe4 x1 in brd_mux_lane_to_slot()
246 * SD1(F) => SLOT4 PCIe1 x1 in brd_mux_lane_to_slot()
247 * SD1(G) => SLOT3 PCIe2 x1 in brd_mux_lane_to_slot()
248 * SD1(H) => SLOT7 SGMII in brd_mux_lane_to_slot()
254 /* SD1(A) => SLOT2 PCIe3 x1 in brd_mux_lane_to_slot()
255 * SD1(B:D) => SLOT7 SGMII in brd_mux_lane_to_slot()
256 * SD1(E) => SLOT1 PCIe4 x1 in brd_mux_lane_to_slot()
257 * SD1(F) => SLOT4 PCIe1 x1 in brd_mux_lane_to_slot()
258 * SD1(G) => SLOT3 PCIe2 x1 in brd_mux_lane_to_slot()
259 * SD1(H) => SLOT7 SGMII in brd_mux_lane_to_slot()