4  * SPDX-License-Identifier:	GPL-2.0+
66 	struct cpu_type *cpu = gd->arch.cpu;  in fsl_ddr_board_options()
72 	if (!pdimm->n_ranks)  in fsl_ddr_board_options()
81 	while (pbsp->datarate_mhz_high) {  in fsl_ddr_board_options()
82 		if (pbsp->n_ranks == pdimm->n_ranks &&  in fsl_ddr_board_options()
83 		    (pdimm->rank_density >> 30) >= pbsp->rank_gb) {  in fsl_ddr_board_options()
84 			if (ddr_freq <= pbsp->datarate_mhz_high) {  in fsl_ddr_board_options()
85 				popts->clk_adjust = pbsp->clk_adjust;  in fsl_ddr_board_options()
86 				popts->wrlvl_start = pbsp->wrlvl_start;  in fsl_ddr_board_options()
87 				popts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2;  in fsl_ddr_board_options()
88 				popts->wrlvl_ctl_3 = pbsp->wrlvl_ctl_3;  in fsl_ddr_board_options()
100 		       pbsp_highest->datarate_mhz_high);  in fsl_ddr_board_options()
101 		popts->clk_adjust = pbsp_highest->clk_adjust;  in fsl_ddr_board_options()
102 		popts->wrlvl_start = pbsp_highest->wrlvl_start;  in fsl_ddr_board_options()
103 		popts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2;  in fsl_ddr_board_options()
104 		popts->wrlvl_ctl_3 = pbsp->wrlvl_ctl_3;  in fsl_ddr_board_options()
110 	      pbsp->n_ranks, pbsp->datarate_mhz_high, pbsp->rank_gb);  in fsl_ddr_board_options()
112 	      pbsp->clk_adjust, pbsp->wrlvl_start, pbsp->wrlvl_ctl_2);  in fsl_ddr_board_options()
113 	debug("wrlvl_ctrl_3 0x%x\n", pbsp->wrlvl_ctl_3);  in fsl_ddr_board_options()
116 	 * Factors to consider for half-strength driver enable:  in fsl_ddr_board_options()
117 	 *	- number of DIMMs installed  in fsl_ddr_board_options()
119 	popts->half_strength_driver_enable = 1;  in fsl_ddr_board_options()
123 	popts->wrlvl_override = 1;  in fsl_ddr_board_options()
124 	popts->wrlvl_sample = 0xf;  in fsl_ddr_board_options()
129 	popts->rtt_override = 0;  in fsl_ddr_board_options()
132 	popts->zq_en = 1;  in fsl_ddr_board_options()
134 	/* DHC_EN =1, ODT = 75 Ohm */  in fsl_ddr_board_options()
136 	popts->ddr_cdr1 = DDR_CDR1_DHC_EN | DDR_CDR1_ODT(DDR_CDR_ODT_80ohm);  in fsl_ddr_board_options()
137 	popts->ddr_cdr2 = DDR_CDR2_ODT(DDR_CDR_ODT_80ohm) |  in fsl_ddr_board_options()
140 	popts->ddr_cdr1 = DDR_CDR1_DHC_EN | DDR_CDR1_ODT(DDR_CDR_ODT_75ohm);  in fsl_ddr_board_options()
141 	popts->ddr_cdr2 = DDR_CDR2_ODT(DDR_CDR_ODT_75ohm);  in fsl_ddr_board_options()
143 	/* optimize cpo for erratum A-009942 */  in fsl_ddr_board_options()
144 	popts->cpo_sample = 0x5f;  in fsl_ddr_board_options()
150 	if (cpu->soc_ver == SVR_T1023)  in fsl_ddr_board_options()
151 		popts->data_bus_width = DDR_DATA_BUS_WIDTH_32;  in fsl_ddr_board_options()
155 	popts->data_bus_width = DDR_DATA_BUS_WIDTH_32;  in fsl_ddr_board_options()
190 	gd->ram_size = dram_size;  in dram_init()